On distributed fault simulation

The authors examine the computational aspects of fault simulation of digital circuits and address issues related to the efficient partitioning of a fault simulation task to a number of subtasks assignable for execution to the nodes of a distributed system. They review the basic concepts involved in the operation of fault simulation. They describe the implementation of a distributed fault simulation facility, called DFSim, using a heterogeneous local area network consisting of a number of workstations with different computing resources and different versions of Unix operating systems     

Deductive Fault Simulation Algorithm Based on Fault Collapsing

The true value simulation is necessary in the critical path tracing fault simulation algorithm.The critical and non-critical inputs can be known after the number of controlling and non-controlling inputs and the criticality of output of every gate are determined.Single output region(SOR)is defined for non-critical lines,so many other non-critical lines can be obtained before fault simulation.The deductive fault simulation algorithm is used to compute the fault list for every possible critical line from bottom to top,which can greatly decrease the length of fault list and simulation time.The cross-sectios is defined to reduce the storage space.The experimental results are given at the end of the paper.     

Accelerated Techniques in Stem Fault Simulation

In order to cope with the most expensive stem fault simulation in fault simulation field.several accelerated techniques are presented in this paper.These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage.With these techniques,the area for stem for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced,so that the entire fault simulation time is substantially decreased.Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns.Especially with the increase of circuit gates,its effectiveness improves obviously.     

Developing a high-level fault simulation standard

Recent developments in deep-submicron technology challenge current integrated circuit testing methods. The increasing complexity of designed systems makes test development more time-consuming. Moreover, nanometer technology introduces new defects or higher data rate errors. To reduce manufacturing costs and time to market, we must develop efficient fault detection and location methods. Using high-level fault simulation stimulates the development of new, fast test-generation algorithms that take into consideration functional features of the system under test or its components. Moreover, all synthesis tools migrate to higher levels, and we believe that this will improve ATPG tools as well     

Fast fault simulation for nonlinear analog circuits

A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.     

机械系统虚拟样机故障仿真技术研究

指出了传统的将基于实物样机的故障模拟结果用于故障研究的不足,分析了机械系统故障仿真技术研究现状。研究了基于虚拟样机的机械系统故障仿真方法,阐述了虚拟样机故障仿真的过程框架及主要功能。分析了虚拟样机故障仿真的三大关键支撑技术,提出了5种机械系统故障注入方法,指出了机械系统虚拟样机故障仿真技术下一步的研究重点。     

Evaluation of process controller fault tolerance using simulation

The paper presents a study of several alternatives of a fault-tolerant process controller design. We compare controller architectures based on different amount of hardware redundancy with those using time redundancy. The system behaviour is evaluated by means of a process-oriented simulation model enabling software injection of faults. As an overall measure of controller design quality (which includes both performance and reliability) we use the numerical error of the output. The results obtained on the model are used to show the dependence of the output error upon the relative speed of computation and upon the rate of faults damaging the data. Thus for every set of parameters, a system configuration which gives the best results, can be determined.     

基于地铁线路的ATS仿真系统故障仿真的研究与设计

近年来,随着国内轨道交通的迅猛发展,城市轨道交通线路日益错综复杂。这使得城市对轨道交通ATC的操作员需求日益增大,对轨道交通工作人员的操作水平要求也越来越高。对此,从之前设计的轨道交通ATS仿真平台出发,收集各种ATS日常运营中的故障,进行设计与仿真。立足于培训操作人员的常规操作,此仿真设计能进一步提高操作人员应对突发状况和故障情形的动手能力,为轨道交通的正常安全运行提供更充分的保障。     

Effect of fault distribution and execution patterns on fault exposure in software: a simulation study

Execution patterns and fault distribution characteristics of a program will affect the failure process and thus reliability estimates. The failure process of a software system is influenced by many factors, and traditional software reliability engineering has found it difficult to isolate the effect of each individual factor. A simulation approach is used to investigate the effects of fault distribution, execution pattern and program structure on software reliability estimates. A reliability simulation environment (RSIM) is extended by introducing variable fault distribution patterns in its code generation phase. Flow control points allow varying the execution frequency of different parts of a program. The simulation results show that fault distribution patterns and execution patterns have dramatic effects on fault exposure rate. If the fault distribution is non‐uniform, a non‐uniform code execution exposes faults more efficiently and effectively than uniform execution. Results also show that the structure of a program affects fault exposure rate and testing time required. Copyright © 2000 John Wiley & Sons, Ltd.     

基于仿真的通用模拟电路故障知识获取平台

故障知识获取是基于知识的模拟电路故障诊断方法的瓶颈问题。总结了通过故障仿真获取模拟电路故障知识的一般过程,简要描述了知识获取自动化的方法,提出建立通用模拟电路故障知识获取平台的方案,并对其主要组成部分和功能进行了详细描述。该平台能自动穷举电路所有可能的故障,调用外部电路仿真软件进行仿真,从仿真结果提取故障知识并加以简化,形成结构化的故障知识库。实验结果证实其可行性。     

数字集成电路老化故障高精度预测方法仿真

针对传统数字集成电路老化故障预测方法耗时较长、结果误差较大问题,提出一种新的数字集成电路老化故障高精度预测方法。该方法对数字集成电路中存在的信号进行滤波处理,去除噪声信号和冗余信号,分析滤波处理后数字集成电路特征,得到数字集成电路漏电流变化。在此基础上,分析数字集成电路中漏电流变化、阈值电压变化和延迟变化三者之间的关系,进而通过启发式算法完成数字集成电路老化程度的分类,实现数字集成电路老化故障的预测。实验结果表明,所提方法预测效率高、准确率高。     

LDO自激振荡故障的仿真建模方法研究

借助频域傅里叶分析的方法 ,对传统PMOS结构LDO系统的稳定性进行了仿真建模方法研究,阐述了引起环路不稳定的因素及其影响机制。结合一例LDO自激振荡故障的分析,指出故障发生的原因和相应的处理措施。     

Application of fuzzy logic in resistive fault modeling and simulation

Real defects (e.g., resistive stuck at or bridging faults) in very large-scale integration (VLSI) circuits cause intermediate voltages which cannot be modeled as ideal shorts. In this paper, we first show that the traditional zero-resistance model is not sufficient for fault simulation. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate level. Our method uses Takagi-Sugeno (TS) fuzzy system to accurately model digital VLSI circuits and produces much more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test-pattern statistics for the ISCAS85 benchmarks.     

Hierarchical simulation approach to accurate fault modeling forsystem dependability evaluation

This paper presents a hierarchical simulation methodology that enables accurate system evaluation under realistic faults and conditions. In this methodology, effects of low-level (i.e., transistor or circuit level) faults are propagated to higher levels (i.e., system level) using fault dictionaries. The primary fault models are obtained via simulation of the transistor-level effect of a radiation particle penetrating a device. The resulting current bursts constitute the first-level fault dictionary and are used in the circuit-level simulation to determine the impact on circuit latches and flip-flops. The latched outputs constitute the next level fault dictionary in the hierarchy and are applied in conducting fault injection simulation at the chip-level under selected workloads or application programs. Faults injected at the chip-level result in memory corruptions, which are used to form the next level fault dictionary for the system-level simulation of an application running on simulated hardware. When an application terminates, either normally or abnormally, the overall fault impact on the software behavior is quantified and analyzed. The system in this sense can be a single workstation or a network. The simulation method is demonstrated and validated in the case study of Myrinet (a commercial, high-speed network) based network system     

变电站智能故障仿真系统实现

仿真变电站以先进的计算机技术构建了一个“真实”、“节能”的变电站，系统采用人工智能技术和基于HLA（高层体系结构）的分布交互式仿真技术相结合的方法，研究开发变电站智能故障仿真系统，系统收集了大量变电站事故类型，如倒闸操作失误、运行中意外事故使保护动作及单相接地等异常情况，并对这些常见现象进行仿真模拟，软件采用平台设计，在画面上进行操作和事故处理时，模拟声音动画，增强了真实感。     

城市交通交叉口故障检测仿真研究

研究城市平面交叉路口的安全评价的问题,由于车流量增加,系统存在随机性,影响故障准确检测.传统的故障检测存在着小样本、大区域、长周期和低信度等缺陷,表现为对小区域地点安全评价的不适应性.同时传统的数据分析方法对于高维非正态,非线性数据分析很难收到很好效果,导致评价可信度低、识别度低等.为了解决以上问题,提出交通冲突技术与投影寻踪分类模型(PPC)的安全评价模型,应用到城市平面交叉口的交通安全评价中,并结合实例进行了应用,得出了昆明市十三个交叉路口的安全级别.经实验证明,改进模型结果合理具有快速、定量分析的优点,避免了权重确定的人为干扰影响故障评价的有效性与时间性问题,为交叉口故障检测优化设计提供了一条新的方法和思路.     

Analysis of non-Markovian repairable fault trees through rare event simulation

Dynamic fault trees (DFTs) are widely adopted in industry to assess the dependability of safety-critical equipment. Since many systems are too large to be studied numerically, DFTs dependability is often analysed using Monte Carlo simulation. A bottleneck here is that many simulation samples are required in the case of rare events, e.g. in highly reliable systems where components seldom fail. Rare event simulation (RES) provides techniques to reduce the number of samples in the case of rare events. In this article, we present a RES technique based on importance splitting to study failures in highly reliable DFTs, more precisely, on a variant of repairable fault trees (RFT). Whereas RES usually requires meta-information from an expert, our method is fully automatic. For this, we propose two different methods to derive the so-called importance function. On the one hand, we propose to cleverly exploit the RFT structure to compositionally construct such function. On the other hand, we explore different importance functions derived in different ways from the minimal cut sets of the tree, i.e., the minimal units that determine its failure. We handle RFTs with Markovian and non-Markovian failure and repair distributions—for which no numerical methods exist—and implement the techniques on a toolchain that includes the RES engine FIG, for which we also present improvements. We finally show the efficiency of our approach in several case studies.

     

基于代理的航天器自主运行仿真系统设计与验证系统设计

针对目前航天器自主健康管理功能测试过程中,由于故障模拟手段不足造成测试覆盖率低,测试项目不完备,测试效率低等问题,提出一种基于代理的航天器自主健康故障仿真验证系统设计方案;基于该方案实现的故障仿真系统支持根据通用化航天器自主健康故障检测模型,严格按逻辑和时序,无延迟、持续的向全实物或半实物测试系统自动注入故障状态表征参数,模拟航天器整器或任意分系统、单机、软件的故障状态,模拟弥补了长期以来在实物测试环境下,整器故障模式测试覆盖率低,测试用例复用性差的问题;实践证明,此方法能将测试覆盖率提升至95%以上,并将测试时间缩短至传统方式的1/6,有效提升被测航天器产品可靠性。     

MNFP — a new technique for efficient digital fault simulation

Since digital fault simulation is a costly process, it is important to use very efficient techniques to perform this function. To this end, this study suggests that parallel fault simulators couldbe implemented with a new fault-simulation technique, called MNFP (multiple number of faults per pass). The technique intends to partition the total fault set into a number of fault groups which can be simulated as multiple faults. The fault group mentioned above should be structured such that ‘a test that detects any single fault in the group will detect the group, and conversely, a test that detects a group will detect at least one single fault in the group’. Thus, an initial attempt is made to detect a faulty group, then the single faults inside the group are located. During the required fault-partitioning process, such erratic phenomena as fault-masking effects and fictitious multiple-fault generation must be eliminated for the fault groups to have the required property. Two approaches to fault partitioning are made for this technique of fault simulation: PFP (probabilistic fault partitioning) and MFP (modular fault partitioning). Significant savings in simulation time are expected to be realized from the MNFP technique of fault simulation.     

车载设备故障导致CTCS等级转换的建模与仿真

采用随机Petri网理论对车载故障可能导致列控系统降级的场景和列控系统在不同等级之间发生转换的场景进行了研究,以保证并提高列车运行环境的安全性。在模型中,对可能导致车载设备故障的三种因素：传输错误、越区切换、连接丢失所引发的车载设备和备用车载设备均故障所引发降级的场景,进行了建模和分析;并在降级场景发生后,列控设备通过尝试连接GSM-R无线网络升级为CTCS-3级进行了建模和分析。用TimeNet4.0平台对模型的正确性进行了仿真,得出了该模型在各种场景发生的概率分布曲线,对CTCS-3降级运行进行了定量与定性分析。