共查询到20条相似文献,搜索用时 125 毫秒
1.
2.
在低信噪比条件下检测出直接序列扩频(DSSS)信号后,要恢复出原始信息,估计出扩频码序列是非常关键的,因此有必要研究DSSS信号的扩频码序列估计算法。提出了一种基于改进的协方差矩阵迭代算法应用于估计扩频码序列。理论分析和计算机仿真实验都表明了该算法能在低信噪比下估计出扩频码序列,与其他一些扩频码序列估计算法如基于投影子空间的算法、基于神经网络的算法相比,具有运算量更小等优势。 相似文献
3.
针对低信噪比下同步多用户非周期长码直扩信号的扩频序列估计问题, 提出了一种基于嵌套迭代最小二乘投影算法的扩频序列估计方法.首先, 将同步多用户非周期长码直扩信号等效为含有缺失数据的相应的短码直扩信号.然后, 利用最大似然估计理论对相应的短码直扩信号进行数学分析, 构建扩频序列估计的数学模型.最后, 利用一种嵌套迭代最小二乘投影算法来实现扩频序列的估计.研究表明, 该算法在低信噪比(小于-10 dB)情况下, 对多用户(多达10路)扩频序列的估计有着良好的性能表现. 相似文献
4.
带内窄带脉冲干扰会对直接序列扩频信号估计性能产生较大的影响,针对此问题,提出了一种抑制窄带脉冲干扰并对扩频码序列及周期的盲估计算法。采用最大熵概率密度谱估计算法估计出接收信号的概率密度谱,进而用估计的概率密度谱设计滤波函数对信号滤波来抑制窄带脉冲干扰。利用二次谱算法对扩频码周期进行估计并通过 Viterbi 算法对扩频序列进行提取。仿真实验表明,该算法不仅能抑制较强的窄带脉冲干扰,而且能在无先验信息的条件下估计出扩频信号的扩频码周期及序列等信息,从而获知直扩通信中所传输的码元序列。 相似文献
5.
短码DS-SS信号扩频序列及信息序列联合盲估计方法 总被引:1,自引:0,他引:1
研究了短码DS-SS信号的扩频序列及信息序列联合盲估计问题。首先,利用双信息符号周期、间隔一信息符号周期的时间窗对接收信号进行重组,并形成接收信号矩阵。然后,利用奇异值分解联合盲估计信号的扩频序列与信息序列。该算法在失步时间未知、低信噪比条件下利用单一矢量空间盲估计扩频序列和信息序列。不但不受扩频序列类型的限制,而且避免了传统特征值分解盲估计算法利用2个矢量空间组合扩频序列时存在的相位模糊问题,提高了盲估计性能。最后仿真验证了算法的有效性。 相似文献
6.
7.
8.
对经典扩频信号信噪比(SNR)估计算法进行分析,提出了一种新的适用于扩频通信系统中频扩频信号信噪比估计算法。该算法在时域估计信号总功率,频域估计噪声功率,时频结合估计出中频扩频信号SNR。在加性高斯白噪声(AWGN)信道下,Matlab仿真结果表明该算法估计精度高,估计范围广及估计下限低。 相似文献
9.
10.
11.
针对直扩序列码分多址(DS-CDMA)系统多用户检测的问题,提出了一种基于性能指标(PI)变步长EASI算法信息码与伪码盲估计的算法.该算法在比较盲源分离(BSS)和DS-CDMA系统模型的基础上,用自适应的方法估计混合矩阵进而估计出伪码,并利用分离矩阵分离观测信号从而估计出信息码.另外,该算法利用PI值来调整步长,使算法收敛速度和稳定性能达到一个理想平衡点.实验结果显示,该算法具有很好的抗多址干扰(MAI)的能力,伪码和信息码的误码率分别在-10 dB和0 dB时达到10-2以下;对不同用户数,5dB时所有扩频码被完全正确检测的概率几乎都在80%以上. 相似文献
12.
数字IC可测性设计和自动测试生成技术 总被引:2,自引:0,他引:2
描述了一种自动局部扫描可测性设计方法,该方法在电路内部提供附加逻辑,把时序元件串成一条扫描通路,辅以适当的控制信号,使时序元件和组合元件分离开,从而达到可测试的目的,介绍了一种改进的PODEM测试生成算法和一种基于模拟的测试生成方法,该方法能较好处理时序电路的测试生成问题。 相似文献
13.
14.
15.
中频数字化扩频测距系统的实现 总被引:1,自引:1,他引:0
给出了统一扩频、统一信道模式的中频数字化扩频测距系统的实现方案。该系统的载波与伪随机码的捕获采用了FFT辅助捕获技术,载波的跟踪采用了数字CPAFC环路牵引、数字COSTAS环路精确跟踪技术,可以有效克服多普勒频移对系统性能的影响。GOLD码跟踪采用的是数字DLL环路,利用该扩频码与截断m序列之间具有的同速率、倍周期的关系,在GOLD码同步后引导截断m序列快速同步。讨论了实现1ns恒分辨率、误差为0.01chip的测距方法与测量数据的"置中值"链接方法。 相似文献
16.
A single-chip 100-Mbit/s burst-operation two-tap maximum likelihood sequence estimation (MLSE) equalizer LSI for QPSK signals is introduced. It also supports two-branch diversity combining. Three new techniques are used to realize this fast equalizer LSI: the quantized variable-gain least mean squares (VLMS) algorithm, which has small processing delay with fast convergence characteristics; a simple complex-valued multiplication scheme based on inverting the sign and switching the in-phase and quadrature-phase components; and a parallel structure to minimize the processing delay of path memory. The chip, containing 75 kgates, is manufactured using the 0.45-μm-CMOS gate array process. The supply voltage is 3.3 V. This LSI offers higher processing speed than any other conventional equalizer chip for mobile radio communications 相似文献
17.
Sheng Liu Erdahl D. Ume I.C. Achari A. Gamalski J. 《Components and Packaging Technologies, IEEE Transactions on》2001,24(4):616-624
A novel, noncontact, nondestructive approach for flip chip solder joint quality inspection is presented. In this technique, a pulsed laser generates ultrasound on the chip's surface, exciting the whole chip into a vibration motion. An interferometer was used to measure the vibration displacement of the chip's surface. Because changes in solder joint quality produce a different vibration response, a value, "error ratio," is used to measure the difference between a good chip and a chip with defects. An automatic signal-processing algorithm to calculate the error ratio was developed and implemented, as well as a frequency analysis algorithm. The inspection system was characterized, and results are presented for two cases of flip chips with missing solder balls. Results indicate that a laser ultrasonic/interferometeric system offers great promise for solder bump inspection in flip chip, BGA, chip scale, and micro BGA packages 相似文献
18.
A linear decentralized receiver capable of suppressing multiple-access interference (MAI) for asynchronous direct-sequence code-division multiple-access (DS-CDMA) systems with aperiodic random signature sequences is proposed. Performance bounds on this receiver are also obtained. Using them as performance measures, the problem of chip waveform selection in DS-CDMA systems with the proposed receiver under the near-far scenario is investigated. In particular, the performance of several practical chip waveforms is compared. An LMS-type adaptive algorithm is developed to obtain the parameters needed in the receiver, which only requires the signature sequence and coarse timing information of the desired user 相似文献
19.
A low power 10-bit 250-k sample per second(KSPS) cyclic analog to digital converter(ADC) is presented. The ADC’s offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence.The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator’s offset errors and switched capacitor mismatch errors.With this structure,it has the advantages of simple circuit configuration,small chip area and low power dissipation.The cyclic ADC manufactured with the Chartered 0.35μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate.It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42×0.68 mm~2. 相似文献