一种基于CSA加法器的Montgomery模幂乘硬件实现算法

提出了一种改进的Montgomery模乘和模幂算法,该算法采用5-to-2 CSA加法器来实现Montgomery模乘算法中的超长大数加法。目前使用CSA加法器的其他模乘算法在模乘结果输出时均需要用CPA加法器来处理CSA加法器的输出结果,而本文提出的算法使得模乘运算的输入输出操作数均可采用保留进位形式,避免了进行超长操作数的CPA加法这一耗时的操作,因此显著减少了模乘运算所需时钟周期,提高了数据处理的时间效率,并加快了RSA模幂运算的速度。     

关于Montgomery模乘迭代的可控性分析

在公钥密码实现中,Montgomery模乘扮演着非常重要的角色。本文研究Montgomery模乘(MMM)的迭代控制结构,给出了进行MMM迭代的输入边界控制条件,以及改进的MMM算法。这种扩展的迭代控制条件适合用于复杂求幂的迭代过程,在其边界控制下可直接进行一些加法、减法及乘法等基本运算,而无须模约化处理。给出的模乘迭代算法具有高度的灵活性,可利用来实现安全高效的RSA、ECC等公钥密码体制。     

基于RSA系统的Montgomery算法的改进设计

针对Montgomery算法中模乘模块的CIOS模式提出了一种改进算法。该算法模式比原CIOS模式节省了近一半的操作次数,并且给出了一种优化的硬件实现结构。在保证系统规模较小的基础上采用了两个相同的数据通路以加速运算速度,同时采用了移位寄存器结构进一步简化时序控制的复杂性。此改进算法适用于各种公钥体制的加解密处理器。     

SM2高速双域 Montgomery 模乘的硬件设计

作为由国家密码管理局公布的SM2椭圆曲线公钥密码算法的核心运算,模乘的实现好坏直接决定着整个密码芯片性能的优劣．Montgomery模乘算法是目前最高效也是应用最为广泛的一种模乘算法．本文基于Mont-gomery模乘算法,设计了一种高速,且支持双域（GF（p）素数域和GF（2m ）二进制域）的Montgomery模乘器．提出了新的实现结构,以及一种新型的W allace树乘法单元．通过对模块合理的安排和复用,本设计极大的缩小了时间消耗与硬件需求,节省了大量的资源．实现256位双域模乘仅需0．34μs ．     

一种用于ECC密码体制的模乘器设计

提出了一种基于Montgomery算法的模乘器。与现有结构相比,由于采用了多级流水线的乘法器结构,提高了系统的时钟频率;并通过引入预计算单元,解决了流水线停顿的问题,提高了系统的并行性,减少了所需的时钟数。该模乘器位长233位,基于SMIC 0.18μm最坏工艺的综合结果表明,电路的关键路径最大时延为3.8 ns,芯片面积2 mm2。一次模乘计算只需要108个时钟周期,适合ECC密码体制的应用要求。     

基于Montgomery算法的智能卡RSA密码协处理器

对Montgomery算法进行了改进，提供了一种适合智能卡应用、以RISC微处理器形式实现的RSA密码协处理器。该器件的核心部分采用了两个32位乘法器的并行流水结构，其功能部件是并发操作的，指令执行亦采用了流水线的形式。在10MHz的时钟频率下，加密1024位明文平均仅需3ms，解密平均需177ms。     

Bit-level systolic arrays for modular multiplication

This paper presents bit-level cellular arrays implementing Blakley's algorithm for multiplication of twon-bit integers modulo anothern-bit integer. The semi-systolic version uses 3n(n+3) single-bit carry save adders and 2n copies of 3-bit carry look-ahead logic, and computes a pair of binary numbers (C, S) in 3n clock cycles such thatC+S[0, 2N). The carry look-ahead logic is used to estimate the sign of the partial product, which is needed during the reduction process. The final result in the correct range [0,N) can easily be obtained by computingC+S andC+S–N, and selecting the latter if it is positive; otherwise, the former is selected. We construct a localized process dependence graph of this algorithm, and introduce a systolic array containing 3nw simple adder cells. The latency of the systolic array is 6n+w–2, wherew=n/2. The systolic version does not require broadcast and can be used to efficiently compute several modular multiplications in a pipelined fashion, producing a result in every clock cycle.     

Montgomery算法的研究与实现

分析了Montgomery算法，指出用改进的预计算Montgomery算法实现模幂运算的过程，分析并比较了两种实现模采和模幂乘算法。并分别用C^ 和Modeleim进行仿真，得出仿真测试结果。     

Performance-Scalable Array Architectures for Modular Multiplication

Modular multiplication is a fundamental operation in numerous public-key cryptosystems including the RSA method. Increasing popularity of internet e-commerce and other security applications translate into a demand for a scalable performance hardware design framework. Previous scalable hardware methodologies either were not systolic and thus involved performance-degrading, full-word-length broadcasts or were not scalable beyond linear array size. In this paper, these limitations are overcome with the introduction of three classes of scalable-performance modular multiplication architectures based on systolic arrays. Very high clock rates are feasible, since the cells composing the architectures are of bit-level complexity. Architectural methods based on both binary and high-radix modular multiplication are derived. All techniques are constructed to allow additional flexibility for the impact of interconnect delay within the design environment.     

使用改进的心动阵列结构实现RSA 公共密钥算法

本文介绍了一种RSA算法的电路实现结构。该结构是对心动阵列结构的改进，对心动阵列结构的核心模块长加法模块进行了循环复用，在大幅度降低电路面积的情况下，运算速度没有明显的降低。用Verilog描述了整个设计，并在FPGA上验证了设计的正确性。     

A Systolic, High Speed Architecture for an RSA Cryptosystem

An architecture based on the RSA public key cryptography algorithm is presented. The circuit includes two components, one for modular squaring and one for modular multiplication. Each component is based on the Montgomery algorithm and implements the modular operations using two modified serial-parallel multipliers. A full modular exponentiation is completed every n(n + 3) clock cycles. All circuits are systolic, operate with 100% efficiency and their maximum combinational delay is equal to one gated Full-Adder. Thus, high-speed performance is achieved while the low cell hardware complexity enables an efficient VLSI implementation.     

CSSA-低功耗Montgomery模乘的环形脉动阵列

文章提出了一种环形脉动阵列CSSA（Circular Structured Systolic Array），用于实现Montgomery模乘算法MMM（Montgomery Modular Multiplication）。该阵列采用循环结构，迭代计算。仿真结果表明，与基于一维脉动阵列的MMM硬件实现相比，该结构牺牲了运算时间，但是降低了功耗和芯片面积（本文实现的两个例子，功耗和芯片面积均减少了约97％）。并且，处理单元的数量可配置，以平衡速度和功耗。     

基于有符号数字系统的Montgomery模逆算法及其硬件实现

 在椭圆曲线密码中,模逆运算是有限域运算中最复杂、最耗时且硬件实现难度最大的运算.本文在Kaliski算法的基础上,提出了基于有符号数字系统的Montgomery模逆算法,它支持素数域和二进制域上任意多精度参数的求模逆运算.据此算法,设计了相应的硬件结构方案,并给出了面积复杂度和时间复杂度分析.仿真结果表明,相比于其它模逆算法硬件设计方案,本文提出的基于有符号数字系统的Montgomery模逆算法在运算速度、电路面积、灵活性等方面具有显著的优越性.     

双有限域模乘和模逆算法及其硬件实现

有限域上的模乘和模逆运算是椭圆曲线密码体系的两个核心运算。该文在Blakley算法的基础上提出一种radix-4快速双有限域模乘算法,该算法采用Booth编码技术将原算法的迭代次数减少一半,并利用符号估计技术简化约减操作;在扩展Euclidean求逆算法的基础上提出一种能够同时支持双有限域运算的高效模逆算法,该算法不仅避免了大整数比较操作,而且提高了算法在每次迭代过程中的移位效率。然后针对这两种算法特点设计出一种能够同时完成双有限域上模乘和模逆操作的统一硬件结构。实现结果表明：256位的模乘和模逆统一硬件电路与同类型设计相比较,在电路面积没有增加的情况下,模乘运算速度提高68%,模逆运算的速度也提高了17.4%。     

Fast,compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications

In this paper, the primitive common-multiplicand Montgomery modular multiplication is developed for modular exponentiation. Together with Montgomery powering ladder, a fast, compact and symmetric modular exponentiation architecture is proposed for hardware implementation. The architecture consists of one group of processing elements along the central line and two symmetric groups of accumulation units on two sides. The central elements perform modular reductions, while the symmetric units on both sides accumulate the modular multiplication results. A feedforwarding architecture is employed to decrease the latency between processing elements, in parallel with the word-based accumulation units, which are also pipelined. Meanwhile, due to the symmetric architecture and Montgomery powering ladder, the modular exponentiation is immune from fault and simple power attacks. Implemented in FPGA platform, the performance of our proposed design outperforms most results so far in the literature.     

一种Montgomery模乘的硬件算法及其实现

采用大数的高基表示方法对原 Montgomery算法进行了改进 ,提出了一种高效的面向硬件的计算 Montgomery积的算法 ,按照该算法实现的硬件具有较低的复杂度和较高的处理速度 ,并且利用 CSMC的 0 .6 μm CMOS标准单元库实现了 5 1 2位的 Montgomery模乘器。该模乘器约含480 0 0等效门 ,面积约为 3 mm× 3 mm,最高工作时钟频率可达 40 MHz,完成 5 1 2位 Montgomery模乘需要 3 4 1个时钟周期     

基于二进制Edwards曲线的椭圆曲线加密多标量乘结构设计与实现

标量乘及多标量乘算法是影响椭圆曲线密码系统性能的关键.基于二进制Edwards曲线提出并实现了一种新型的椭圆曲线标量乘法器.由于Edwards曲线的完备性,这种乘法器可对曲线上任意一点进行计算,而不用区分倍乘或者负元,实现较简单,有很高的运算速度和很强的抗侧信道攻击的能力.     

一种RISC微处理器的快速乘除法运算设计与实现

定点尾数乘除法器是相应32位浮点运算的核心部件,针对工控应用,本文采用半定制方法完成了设计并且采用TSMC0.18微米工艺实现.乘法器采用基4Booth编码,通过对符号位、隐含位的处理减少了部分积的生成,并在Wallace树求和过程中,引入4∶2压缩器,加快了求和速度.除法器采用改进的SRT算法,引入商位猜测、部分余并行计算、商位修正值选择电路.乘除法器均采用了进位保留加法器提高运算速度.后端物理实现表明,乘除法器的频率分别可到227 MHz,305 MHz,整体设计具有简洁、快速、计算准确的特征.     

Adaptive Magnetoactive Soft Composites for Modular and Reconfigurable Actuators

Magnetoactive soft materials, typically composed of magnetic particles dispersed in a soft polymer matrix, are finding many applications in soft robotics due to their reversible and remote shape transformations under magnetic fields. To achieve complex shape transformations, anisotropic, and heterogeneous magnetization profiles must be programmed in the material. However, once programmed and assembled, magnetic soft actuators cannot be easily reconfigured, repurposed, or repaired, which limits their application, their durability, and versatility in their design. Here, magnetoactive soft composites are developed from squid-derived biopolymers and NdFeB microparticles with tunable ferromagnetic and thermomechanical properties. By leveraging reversible crosslinking nanostructures in the biopolymer matrix, a healing-assisted assembly process is developed that allows for on-demand reconfiguration and magnetic reprogramming of magnetoactive composites. This concept in multi-material modular actuators is demonstrated with programmable deformation modes, self-healing properties to recover their function after mechanical damage, and shape-memory behavior to lock in their preferred configuration and un-actuated catch states. These dynamic magnetic soft composites can enable the modular design and assembly of new types of magnetic actuators, not only eliminating device vulnerabilities through healing and repair but also by providing adaptive mechanisms to reconfigure their function on demand.