原子层沉积超薄氮化铝薄膜的椭圆偏振光谱法表征

采用原子层沉积(ALD)工艺在硅衬底上生长了35 nm以下不同厚度的超薄氮化铝(AlN)晶态薄膜。利用椭圆偏振光谱法在波长275~900 nm内测量并拟合薄膜的厚度及折射率和消光系数等光学参数。利用原子力显微镜(AFM)表征AlN晶粒尺寸随生长循环次数的变化,计算得到薄膜表面粗糙度并用于辅助椭偏模型拟合。针对ALD工艺特点建立合适的椭偏模型,可获得AlN超薄膜的生长速率为0.0535 nm/cycle,AlN超薄膜的折射率随着生长循环次数的增加而增大,并逐渐趋于稳定,薄膜厚度为6.88 nm时,其折射率为1.6535,薄膜厚度为33.01 nm时,其折射率为1.8731。该模型为超薄介质薄膜提供了稳定、可靠的椭圆偏振光谱法表征。     

Ultra Thin Film Encapsulation of Organic Light Emitting Diode on a Plastic Substrate

We have carried out the fabrications of a barrier layer on a polyethersulfon (PES) film and organic light emitting diode (OLED) based on a plastic substrate by means of atomic layer deposition (ALD). Simultaneous deposition of 30 nm AlO_x film on both sides of the PES film gave a water vapor transition rate (WVTR) of 0.062 g/m²/day (@38°C, 100% R.H.). Further, the double layer of 200 nm SiNx film deposited by plasma enhanced chemical vapor deposition (PECVD) and 20 nm AlOx film by ALD resulted in a WVTR value lower than the detection limit of MOCON. We have investigated the OLED encapsulation performance of the double layer using the OLED structure of ITO / MTDATA (20 nm) / NPD (40 nm) / AlQ (60 nm) / LiF (1 nm) / Al (75 nm) on a plastic substrate. The preliminary life time to reach 91% of the initial luminance (1300 cd/m²) was 260 hours for the OLED encapsulated with 100 nm of PECVD‐deposited SiNx and 30 nm of ALD‐deposited AlO_x.     

Gas Sensing of NiO‐SCCNT Core–Shell Heterostructures: Optimization by Radial Modulation of the Hole‐Accumulation Layer

Hierarchical core–shell (C–S) heterostructures composed of a NiO shell deposited onto stacked‐cup carbon nanotubes (SCCNTs) are synthesized by atomic layer deposition (ALD). A film of NiO particles (0.80–21.8 nm in thickness) is uniformly deposited onto the inner and outer walls of the SCCNTs. The electrical resistance of the samples is found to increase of many orders of magnitude with the increasing of the NiO thickness. The response of NiO–SCCNT sensors toward low concentrations of acetone and ethanol at 200 °C is studied. The sensing mechanism is based on the modulation of the hole‐accumulation region in the NiO shell layer upon chemisorption of the reducing gas molecules. The electrical conduction mechanism is further studied by the incorporation of an Al₂O₃ dielectric layer at NiO and SCCNT interfaces. The investigations on NiO–Al₂O₃–SCCNT, Al₂O₃–SCCNT, and NiO–SCCNT coaxial heterostructures reveal that the sensing mechanism is strictly related to the NiO shell layer. The remarkable performance of the NiO–SCCNT sensors toward acetone and ethanol benefits from the conformal coating by ALD, large surface area of the SCCNTs, and the optimized p‐NiO shell layer thickness followed by the radial modulation of the space‐charge region.     

Enhancement in thermal stability of atomic layer deposited HfO2 films by using top Hf metal layer

A thin (∼ 0.5 nm) layer of Hf metal was deposited on an atomic layer deposited (ALD) HfO₂ film by the DC sputtering method. X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy analyses showed that the Hf metal layer transformed into HfO₂ during the post-deposition annealing process. It appears that the HfO₂ layer formed by the oxidation of Hf metal provided the underlying ALD HfO₂ layer with the nucleation sites necessary to decrease the grain-boundary density of the crystallized HfO₂ film. The decrease in the grain-boundary density resulted in a reduction in the Hf-silicate formation and interfacial layer growth during post deposition annealing. This eventually resulted in a smaller increase in the capacitance equivalent thickness (CET) and high-k characteristics in the CET vs. leakage current density curve even after post deposition annealing at 1000 °C.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Investigation of the Process of Plasma Through Etching of HkMG Stack of Nanotransistor with a 32-nm Critical Dimension

The processes of plasma etching of stack layers to form a structure of a metal gate of a nanoscale transistor with a dielectric with a high level of dielectric permittivity (HkMG) are investigated. A resist mask formed by fine-resolution electron-beam lithography is used in the etching. The plasma etching of the stack’s layers is carried out in one technological etching cycle without a vacuum break. The sequential anisotropic etching process of the stack of polysilicon, tantalum nitride, and hafnium nitride, as well as the etching process of the gate insulator based on hafnium oxide with a high degree of selectivity in relation to the underlying crystalline silicon, which guarantees the complete removal of the layer of hafnium oxide and the minimal loss of the silicon layer (not more than 0.5 nm), is investigated.     

ALD氧化铝薄膜介电性能及其在硅电容器的应用

硅基高密度电容器是利用半导体3D深硅槽技术和应用高介电常数(高K)材料制作的电容。相比钽电容和多层陶瓷电容(MLCC),硅基电容具有十年以上的寿命、工作温度范围大、容值温度系数小以及损耗低等优点。文章研究原子层沉积(ALD)制备的Al2O3薄膜的介电特性,通过优化ALD原子沉积温度和退火工艺,发现在沉积温度420℃和O3气氛退火5 min下,ALD生长的Al2O3薄膜击穿强度可大于0.7 V/nm,相对介电常数达8.7。制成的硅基电容器电容密度达到50 nF/mm2,漏电流小于5 nA/mm2。     

Monolayer-precision fabrication of mixed-organic–inorganic nanohybrid superlattices for flexible electronic devices

We report a low-temperature fabrication of mixed-organic–inorganic nanohybrid superlattices for high-k thin stable gate dielectrics on flexible substrates. The self-assembled organic layers (SAOLs) were grown by repeated sequential adsorptions of CC-terminated alkylsilane and metal (Al or Ti) hydroxyl with ozone activation, which was called “molecular layer deposition (MLD)”. The MLD method is a self-controlled layer-by-layer growth process under vacuum conditions, and is perfectly compatible with the atomic layer deposition (ALD) method. The TiO₂ and Al₂O₃ inorganic layers were grown by ALD, which relies on sequential saturated surface reactions resulting in the formation of a monolayer in each sequence and is a potentially powerful method for preparing high quality multicomponent superlattices. The MLD method combined with ALD (MLD–ALD) was applied to fabricate SAOLs-Al₂O₃–SAOLs-TiO₂ nanohybrid superlattices on polycarbonate substrates with accurate control of film thickness, large-scale uniformity, excellent conformality, good reproducibility, multilayer processing capability, sharp interfaces, and excellent film qualities at relatively low temperature. The prepared ultrathin nanohybrid films exhibited good thermal and mechanical stability, good flexibility, excellent insulating properties, and relatively high dielectric constant k (6–11). The MLD–ALD method is an ideal fabrication technique for various flexible electronic devices.     

基于SEM-SPM原位纳米压痕超薄铜薄膜弹性模量研究

本文利用自主研发的扫描电子显微镜-扫描探针显微镜联合测试系统(SEM-SPM),研究了直流磁控溅射(DCMS)和原子层沉积(ALD)两种成膜方式对40、60和80 nm超薄铜薄膜弹性模量的影响.基于赫兹理论和King模型的计算结果表明,利用DCMS得到不同厚度铜薄膜的弹性模量值在(95±2)Gpa~(125±4)GPa之间,而通过ALD得到的铜薄膜弹性模量值在(99±2)Gpa~(154±6)GPa之间.对比分析可知,不同厚度的铜薄膜弹性模量比块体铜材料的弹性模量(90 GPa)大6%~71%,且通过两种不同方式沉积得到的铜薄膜弹性模量值都随着薄膜厚度的增加而减小,表现出明显的尺寸效应.而且对于同一厚度的铜薄膜,利用ALD沉积的弹性模量比DCMS的大4.2%~23.2%,由透射电子显微图像对比分析可知,前者的平均晶粒尺寸是后者的60%,纳米晶粒小尺寸效应可能是薄膜弹性模量增大的原因.     

Top injection reactor tool with in situ spectroscopic ellipsometry for growth and characterization of ALD thin films

Ta-N based thin films were grown by thermal atomic layer deposition (ALD) with an alternating supply of the reactant source TBTDET (tert-butylimidotris(diethylamido)tantalum) and NH₃ (ammonia). The films were deposited using a newly designed and constructed atomic layer deposition prototype tool combined with several in situ metrology. It was observed that thin films were successfully deposited on a 300 mm Wafer with a saturated growth rate of approximately 0.55 Å/cycle at 270 °C. The as deposited films resulted in the formation of Ta(C)N consisting of 38 at% Ta, 32 at% N and 10 at% C. With in situ spectroscopic ellipsometry (SE) the growing behaviour of the film was investigated and compared to atomic force microscopy (AFM) images.     

TDDB improvement by optimized processes on metal-insulator-silicon capacitors with atomic layer deposition of Al_2O_3 and multi layers of TiN film structure

A metal-insulator-silicon （MIS） capacitor with hemi-spherical grained poly atomic layer deposition （ALD） deposited Al2O3 and multi-layered chemical vapor deposition （CVD） TiN structure is fabricated. The impact of the deposition process and post treatment condition on the MIS capacitor＇s time-dependent dielectric breakdown （TDDB） performance is also studied. With an optimized process, it is confirmed by Auger electron spectroscopy and secondary ion mass spectrometry analysis that the Al（CH3）3/O3-based ALD Al2O3 dielectric film is carbon free and the hydrogen content is as low as 9 × 1019 cm-3. The top electrode TiN is obtained by multi-layered TiCl4/NH3 CVD deposited TiN followed by 120 s post NH3 treatment after each layer. This has higher diffusion barrier in preventing impurity diffusion through TiN into the Al2O3 dielectric due to its smaller grain size. As shown in energy dispersive X-ray analysis, there is no chlorine residue in the MIS capacitor structure. The leakage current of the capacitor is lower than 1 × 10-12 A/cm2. No early failures under stress conditions are found in its TDDB test. The novel MIS capacitor is proven to have excellent reliability for advanced DRAM technology.     

等离子体增强原子层沉积原理与应用

等离子体增强原子层沉积(PEALD)是一种低温制备高质量超薄薄膜的有效手段,近年来正受到工业界和学术界广泛的关注。简要介绍了PEALD的发展历史和生长原理。描述了PEALD常见的三种设备构造:自由基增强原子层沉积、直接等离子体沉积和远程等离子体沉积,比较了它们的优缺点。着重评述了PEALD的特点,主要具有沉积温度低、前驱体和生长材料种类广、工艺控制灵活、薄膜性能优异等优势,但也面临着薄膜三维贴合性下降和等离子体损伤等挑战。列举了PEALD的一些重要应用,如在金属薄膜制备、铜互连阻挡层、高介电常数材料、薄膜封裹等领域的应用。最后展望了PEALD的发展前景。     

Atomic layer deposition of tantalum oxide thin films for their use as diffusion barriers in microelectronic devices

Atomic Layer Deposition (ALD) was used for the deposition of tantalum oxide thin films in order to be integrated in microelectronic devices as barrier to copper diffusion. The influence of deposition temperature, number of cycles and precursor pulse time on the film growth was discussed. The conformity of thinnest deposited films was shown. Copper diffusion through ALD Ta₂O₅ thin films, 20 nm in thickness, was investigated, for three temperatures from 600 to 800 °C, using X-ray Photoelectron Spectroscopy. The failure of such films was detected after a thermal treatment at 700 °C.     

Effects of deposition temperature on the oxidation resistance andelectrical characteristics of silicon nitride

A study was made of the effects of deposition temperature on the oxidation resistance and electrical characteristics of silicon nitride. It was found that silicon nitride below a certain limit thickness has no oxidation resistance. This threshold falls as the deposition temperature is lowered. 3-nm-thick silicon nitride deposited at 600°C has sufficient oxidation resistance For wet oxidation at 850°C, while 5 nm film deposited at 750°C has no oxidation resistance. The electrical characteristics also improve as the deposition temperature is lowered. 6-nm-thick silicon nitride deposited at 600°C shows a TDDB lifetime that is about two orders longer than that of 6-nm-thick silicon nitride deposited at 700°C. It was also found that the silicon nitride transition layer which is deposited at the initial stage of deposition influences the oxidation resistance and electrical characteristics of thin silicon nitride. It was concluded that lowering the deposition temperature reduces the influence of the transition layer and improves the oxidation resistance and electrical characteristics of thin silicon nitride     

Effects of thermal annealing on the charge localization characteristics of HfO2/Au/HfO2 stack

To be compatible with the mainstream nano CMOS technology and to further increase the density and to reduce power consumption of non-volatile memory, high-k dielectric will become the major technology option for next generation non-volatile memory technology. To ensure the required retention time and to maintain the scalability of floating gate memory transistor, the charge store in future memory transistor should be accompanied with the high-k insolated metal or conductive clusters, islands, or nano-particles. This work proposes a simple method to fabricate high-k isolated metal cluster array. An HfO₂/Au/HfO₂ stack was first grown by using atomic layer deposition (ALD) and thermal evaporation, respectively, for HfO₂ and Au film deposition. After a high-temperature thermal annealing, a number of HfO₂-buried Au islands with diameter of about 5 to10 nm were obtained. Capacitance–voltage (C–V) measurements show that the charge storage characteristics of the Au-embedded HfO₂ structure were affected greatly by the annealing conditions. Depending on the annealing temperature (it should be governed by thickness of Au layer also), the thermal annealing may lead to the formation of Au islands/clusters, the improvement of HfO₂ blocking property as a result of defect removal, or the deterioration of the blocking property of HfO₂ due to the crystallization of HfO₂ film. Process optimization should be conducted for further improving the charge localization characteristics.     

Electrical properties of sputtered (Ba, Sr)TiO3 thin films prepared by two-step deposition method

The influence of two-step deposition on the electrical properties of sputtered (Ba,Sr)TiO₃ thin films was investigated. BST thin films with thickness 40 nm were deposited by a simple two-step radio frequency-magnetron sputtering technique, where the BST thin film consisted of a seed layer and a main layer. The dielectric constant was strongly dependent on the thickness of seed layer, but there was no dependence on deposition temperature of the seed layer. For a 2 nm seed layer, the dielectric constants were higher by about 29% than those of single-step BST thin films due to higher crystallinity and the leakage current was nearly the same as that of a single-step sample in bias voltage from −2 to 2.5 V. However, an improvement of the dielectric constant was not observed for samples having above 4 nm thick seed layers. A 40 nm thick BST film with 2 nm thick seed layer deposited by a two-step method exhibited a SiO₂ equivalent thickness of 0.385 nm and a leakage current density of 2.74 × 10⁻⁸A/cm²at+1.5V after post-annealing under an atmosphere of flowing N₂ for 30 min at 750°C.     

N_2和NH_3退火对铪铝氧栅介质C-V特性的影响

采用原子层淀积(ALD)的方法在Si(100)衬底上制备了铪铝氧(HfAlO)高介电常数介质,并研究了N2和NH3退火对于介质薄膜的影响。改变原子层淀积的工艺,制备了三组含有不同Al∶Hf原子比的铪铝氧(HfAlO)高介电常数介质。电容电压特性(C-V)测试表明,薄膜的积累电容密度随着薄膜中Al∶Hf原子比的减少而增加。实验表明,用N2和NH3对样品进行淀积后退火,可以减小等效电容厚度(CET)、降低固定正电荷密度以及减小滞回电压,从而有效地提高了介质薄膜的电学特性。     

ZnO for application in photocatalysis: From thin films to nanostructures

In this research work, we report the photocatalytic properties of ZnO synthesized in several forms: ZnO thin films deposited by atomic layer deposition (ALD), ZnO nanofibers synthesized by electrospinnig, and ZnO nanorods realized by chemical bath deposition onto ZnO thin films grown by ALD. The methylene blue was employed as a representative dye pollutant to evaluate the photocatalytic activity of the samples. All the nanostructured materials showed an enhancement of the photocatalytic activity with respect to the thin films. It was found that ZnO nanorods deposited onto 3 nm thin film showed the best photocatalytic activity. The relevance of the results is discussed, opening the route for the application of ZnO in photocatalysis.     

Electrical properties of high-quality ultrathin nitride/oxide stackdielectrics

The electrical properties of ultrathin nitride/oxide (N/O) stack dielectrics (2-4 nm), produced by in-situ jet vapor deposition (JVD), have been studied in some detail. Both theoretical calculation and experimental data show that the leakage current in the N/O stack is substantially lower than that in the single oxide layer of the same equivalent oxide thickness (EOT). When compared to the single nitride layer, the N/O stack yields a lower leakage current in the 3-nm thickness regime. In the 2-nm thickness regime, however, the leakage currents in the single nitride layer and the N/O stack are comparable. The tunneling current in the N/O stack depends not only on the thickness combination of the nitride and the oxide layers, but also on the injection polarity. Other important electrical properties of the N/O stack, including time-dependent-dielectric-breakdown (TDDB), stress-induced leakage current (SILC), carrier trapping, and interface characteristics are also reported. High quality field-effect transistors have been made of the N/O stack, and their properties will be reported     

Atomic layer chemical vapour deposition of copper

Copper films with (1 1 1) texture are of crucial importance in integrated circuit interconnects. We have deposited strongly (1 1 1)-textured thin films of copper by atomic layer deposition (ALD) using [2,2,6,6-tetramethyl-3,5-heptadionato] Cu(II), Cu(thd)₂, as the precursor. The dependence of the microstructure of the films on ALD conditions, such as the number of ALD cycles and the deposition temperature was studied by X-ray diffraction, scanning electron microscopy (SEM), and transmission electron microscopy. Analysis of (1 1 1)-textured films shows the presence of twin planes in the copper grains throughout the films. SEM shows a labyrinthine structure of highly connected, large grains developing as film thickness increases. This leads to low resistivity and suggests high resistance to electromigration.