A low-power inverted ladder D/a converter

Interpolating, dual resistor ladder digital-to-analog converters (DACs) typically use the fine, least significant bit (LSB) ladder floating upon the static most significant bit (MSB) ladder. The usage of the LSB ladder incurs a penalty in dynamic performance due to the added output resistance and switch matrix parasitic capacitance. Current biasing of the LSB ladder addresses this issue by employing active circuitry. We propose an inverted ladder DAC, where an MSB ladder slides upon two static LSB ladders. While using no active components this scheme achieves lower output resistance and parasitic capacitance for a given power budget. We present a 0.35-/spl mu/m, 3.3-V implementation consuming 22-/spl mu/A current with output resistance of 40 k/spl Omega/ and effective parasitic capacitance of 650 fF.     

Design techniques for a low-power low-cost CMOS A/D converter

A 10 bit 200 kHz algorithmic analog-to-digital converter (ADC) was designed to demonstrate design techniques for low-power low-cost CMOS integrated systems. A switched-bias power-reduction technique reduces the total system power by 10%. A layout technique employing extra thin poly-layer lines instead of conventional dummy devices reduces plasma-induced comparator offsets. Based on a standard digital CMOS process with a single poly layer, the ADC adopts metal-to-metal capacitors for internal charge storage. The experimental ADC was fabricated in a 0.6 μm single-poly double-metal n-well CMOS technology, and showed a power consumption of 7 mW and a signal-to-noise-and-distortion ratio (SNDR) of 53 dB at the Nyquist sampling rate with a 3.3 V single supply voltage. The measured differential and integral nonlinearities of the prototype are less than ±0.8 and ±1.8 LSB, respectively     

一种低功耗10位流水线结构的CMOS A/D转换器的设计

本文设计了一种可满足视频速度应用的低电压低功耗10位流水线结构的CMOS A/D转换器.该转换器由9个低功耗运算放大器和19个比较器组成,采用1.5位/级共9级流水线结构,级间增益为2并带有数字校正逻辑.为了提高其抗噪声能力及降低二阶谐波失真,该A/D转换器采用了全差分结构.全芯片模拟结果表明,在3V工作电压下,以20MHz的速度对2MHz的输入信号进行采样时,其信噪失调比达到53dB,功率消耗为28.7mW.最后,基于0.6μm CMOS工艺得到该A/D转换器核的芯片面积为1.55mm2.     

A new successive approximation architecture for low-power low-cost CMOS A/D converter

A new 6-bit 250 MS/s analog-to-digital converter (ADC) is proposed for low-power low-cost CMOS integrated systems. This design is based on an improved successive approximation ADC with a mixed-mode subtracter that minimizes the overall power consumption and system complexity. The experimental results indicate that this ADC works up to 250 MS/s with power consumption less than 30 mW at 3.3 V. Moreover, the operating voltage is scaled down to 0.8 V using a slight adjustment. The ADC occupies only 0.1 mm/sup 2/ with the TSMC 0.35-/spl mu/m single poly quadruple metal (SPQM) CMOS technology. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SoC) circuit designs.     

A low-power stereo 16-bit CMOS D/A converter for digital audio

A low-power 16-bit CMOS D/A (digital/analog) converter for portable digital audio is described. The converter is based on current division. To guarantee monotonicity and a good small-signal reproduction, a dynamic segmentation technique is used. A geometric averaging technique is used to minimize the harmonic distortion of the converter at high signal levels. The dynamic range is 95 dB. The circuit operates in a time-multiplex mode at a sample frequency of 44 kHz in a power supply range of 2.5-5 V and has a power consumption of 15 mW. A 2-μm CMOS technology is used and the active chip area is 5 mm²      

应用于全数字发射机的射频信号发生器

提出了一种应用于全数字发射机的射频信号发生器。设计中采用高速带通ΣΔ调制技术和对系数量化不敏感的有限长单位脉冲冲激响应(FIR)数字滤波技术,在保证速度和精度的同时,有效降低功耗。芯片采用TSMC65nm1P9M GP CMOS工艺实现。测试结果表明,在1.1V电源电压下,芯片可工作在1.408GHz,单频输入带内信噪比(SNR)为53.19dB。输入不同采样频率WCDMA信号时,调制器输出邻信道功率比(ACPR)均满足相关协议要求,最大功耗为32mW。     

A 900-mV low-power ΔΣ A/D converter with 77-dB dynamicrange

The design of a low-voltage and low-power ΔΣ analog-to-digital (A/D) converter is presented. A third-order single-loop ΔΣ modulator topology is implemented with the differential modified switched op-amp technique. The modulator topology has been transformed as to accommodate half-delay integrators. Dedicated low-voltage circuit building blocks, such as a class AB operational transconductance amplifier, a common-mode feedback amplifier, and a comparator are treated, as well as low-voltage design techniques. The influence of very low supply voltage on power consumption is discussed. Measurement results of the 900-mV ΔΣ A/D converter show a 77-dB dynamic range in a 16-kHz bandwidth and a 62-dB peak signal-to-noise ratio for a 40-μW power consumption     

A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter

A low-power switched-current matched filter (MF) for code-division multiple-access (CDMA) systems has been developed. The front-end voltage-to-current (V/I) converter has been eliminated by merging the function into each matching cell utilizing the MOS linear I-V characteristics. A low-power analog-to-digital (A/D) converter has also been developed to establish smooth interfacing to digital back-end processing for a delayed locked loop (DLL) and a RAKE receiver. A proof-of-concept chip was fabricated in a 0.35-μm standard CMOS technology with a measured power consumption of 1.65 mW at 11 Mchip/s with 2-V power supply including the A/D converter.     

A high-speed CMOS image sensor with a 11-bit column-parallel A/D converter

This article presents a high-speed, high-linearity 400 × 320 pixel CMOS image sensor with column parallel ADC. The pixel readout circuit is integrated in the 320 columns at one side of the pixel array and all columns consume 16 mW power provided from the 2.5 V power supply. A technique for accelerating conversion speed using two step single slope structure is developed. This new method has more advantages than conventional ramp ADC from viewpoint of speed and resolution. A prototype 11-bit ADC is implemented in 0.25 μm CMOS technology. Moreover, an overall SNR of 63.8 dB can be achieved at 0.5 Msample/s. The power dissipation of all 320 column-parallel ADCs with the peripheral circuits consumes 76 mW.     

Design and experiments on a high-resolution multi-gigahertzsampling rate superconducting A/D converter

Work towards a high-resolution multi-gigahertz sampling rate A/D converter is presented. A brief review of the overall architecture which consists of a coarse section and an interpolator section is given. Experiments on two designs for the coarse sections are discussed. One is a 6-bit A/D converter built with two-leaf phase tree periodic comparators. Asynchronous beat frequency tests at 2.01 GHz sampling rates indicate this circuit is capable of 6 bits of resolution at 2 GHz input bandwidth. The resolution falls off to about 5 bits at 4 GHz and 4 bits at 6 GHz. The other approach involves two related novel single threshold comparators with large dynamic range. For one of the comparators, dynamic range in excess of 60 db is demonstrated by transfer characteristic and input current noise measurements, while the other showed 54 db of dynamic range. A chain of 15 comparators based on one of the designs has been designed and tested. Asynchronous beat frequency tests at 2.01 GHz sampling rates show a monotonic response for input frequencies up to 8 GHz. Threshold offsets due to flux trapping limited the resolution in this set of experiments to about 5 bits. Experiments on a periodic interpolator circuit based on the two-leaf phase tree comparator are also presented. The results suggest that it should be possible to obtain 10-bits of resolution with this approach     

A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip

This paper presents an impact and low power algorithmic ADC which is implemented on a large scale field programmable analog array chip. The proposed circuit is merely composed of the elements within a single computational analog block (CAB) to minimize the area and parasitic effects. The feedback residue is amplified by a simple operational transconductance amplifier with a gain of \(-\,2\). Therefore, a new algorithm for the conversion process is proposed for this negative gain structure. Furthermore, owing to the floating-gate technique adopted in this work, the parameters and routes of the ADC achieve exceptional reconfigurability. The offset, reset, reference, threshold voltages, and gain all can be adjusted for optimizing the ADC performance. The measured results of the DNL is + 2/? 1 LSB and the INL is + 1.8/? 1.4 LSB, respectively. Under an 8-bit resolution and a 62.5 Hz sampling frequency condition, the measured effective number of bit is 7.6 bits. The total current consumption of the OTAs and FGOTAs is \(1.6\,\upmu\)A under a 2.5 V supply voltage. Each CAB which includes all components, switches, and routings occupies an area of \(400 \times 500\,{\mathrm{mm}}^2\).     

A low-profile low-power converter with coreless PCB isolationtransformer

Very small manually wound transformers for sub-watt DC-DC converters are notorious for their relatively high cost and low reliability. In this paper, an isolated low-profile low-power 8 MHz soft-switching power converter using a coreless printed circuit board (PCB) transformer is described. Coreless PCB transformers eliminate several problems of their core-based counterparts in low-power applications. The diameter of the coreless PCB transformer is merely 0.46 cm. The converter's power output is about 0.5 W with a typical transformer efficiency of 63%. The high-frequency capability, high reliability and the low-profile structure make coreless PCB transformers a viable and attractive option for reliable mega-hertz switching converters and micro-circuits     

A/D和D/A转换器IC

代码转换器提高DSP效率 TLV320AIC10 16位代码转换器提供连续数据传输,可支持DSP自动缓冲单元,减少因缓冲(最高达64kB)不足而引起的中断。该器件特性有每秒22k的采样速率,一个串行接口,增益范围为-36～24dB的可编程增益放大器,一个2:1模拟多路复用器,以及节能备用模式。其它性能包括:工作电压3～5.5V,在采样速率为每秒8k时功耗为39mW。     

Design and simulation of micromechanical thermal converter for RF power sensor microsystem

This paper discusses the thermo-mechanical simulations performed with the aim to optimize the temperature distribution of the microwave power sensor (MPS) microsystem keeping the thermal stress as low as possible. The concept of the absorbed power measurement is based on a thermal conversion, where the dissipated or absorbed RF power is converted into the thermal power, inside a thermally isolated system, so-called the micromechanical thermal converter (MTC) device. A new MTC approach uses a GaAs with an active high electron mobility transistor (HEMT) heater. New technology of low stress polyimide has been used for MTC thermal isolation.By means of thermo-mechanical simulations, we propose a GaAs micromechanical thermal converter design and a layout of the active sensor elements (HEMT heater and a temperature sensor TS) placed on the MTC structure. Spatial temperature distribution, thermal time constant, thermal stress and displacement and the power to temperature characteristics are calculated from the heat distribution. These findings are compared with results of thermo-mechanical measurement of real micromachined MTC devices. The 3-D thermal and thermo-mechanical simulations were performed, using the CoventorWare simulator.     

A rail-to-rail differential quasi-digital converter for low-power applications

This paper presents an ultra low power differential voltage-to-frequency converter (dVFC) suitable to be used as a part of a multisensory interface in portable applications. The proposed dVFC has been designed in 1.2-V 0.18-μm CMOS technology, and it works properly over the whole differential input range (0.6 ± 0.6 V) providing an output frequency range of 0.0–0.9 MHz. The system has been tested for temperature variations from ?40 to +120 °C and supply voltage variations of up to 30 %, being the maximum linearity error in the worse case of 0.017 %. Simulations against common mode voltage variations show a deviation in the output frequency of 0.4 %. This dVFC has power consumption below 60 μW, and it includes an enable terminal that sets the system in a sleep mode (180 nW) while no conversion is request. The dVFC occupies an active area of 250 μm × 150 μm.     

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter

An 800-MHz low-power direct digital frequency synthesizer (DDFS) with an on-chip digital-to-analog (D/A) converter is presented. The DDFS consists of a phase accumulator, two phase-to-sine converters, and a D/A converter. The high-speed operation of the DDFS is enabled by applying parallelism to the phase-to-sine converter and by including a D/A converter in a single chip. The on-chip D/A converter saves delay and power consumption due to interchip interconnections. The DDFS considerably reduces power consumption by using several low-power techniques. The pipelined parallel accumulator consumes only 22% power of a conventional pipelined accumulator with the same throughput. The quad line approximation (QLA) and the quantization and error ROM (QE-ROM) minimize the ROM to generate a sine wave. The QLA saves 4 bits of the sine amplitude by approximating the sine function with four lines. The QE-ROM quantizes the ROM data by magnitude and address and then it stores the quantized values and the quantization errors separately. The ROM size for a 9-bit sine output is only 368 bits. A DDFS chip is fabricated in a 0.35-/spl mu/m CMOS process. It consumes only 174 mW at 800 MHz with 3.3 V. The chip core area is 1.47 mm/sup 2/. The spurious-free dynamic range (SFDR) is 55 dBc.     

A high-frequency and high-resolution fourth-order /spl Sigma//spl Delta/ A/D converter in BiCMOS technology

A high-performance cascaded sigma-delta modulator is presented. It has a new three-stage fourth-order topology and provides functionally a maximum signal to quantization noise ratio of 16 bits and 16.5-bit dynamic range with an oversampling ratio of only 32. This modulator is implemented with fully differential switch-capacitor circuits and is manufactured in a 2-/spl mu/m BiCMOS process. The converter, operated from +/-2.5 V power supply, +/-1.25 V reference voltage and oversampling clock of 48 MHz, achieves 97 dB resolution at a Nyquist conversion rate of 1.5 MHz after comb-filtering decimation. The power consumption of the converter is 180 mW.<>     

A self-calibration method for fast high-resolution A/D and D/Aconverters

Monolithic analog-to-digital (A/D) and digital-to-analog (D/A) converters suffer from the limited accuracy of the available circuit compensators. A self-calibration method allows the correction of the linearity errors of binary-weighted current-source arrays commonly used in high-speed converters. To achieve high-calibration accuracy a modified dual-slope method is used. This makes it possible to implement A/D and D/A converters with a resolution of 14 b or more at a conversion time of less than 15 μs     

A low-power 12-b analog-to-digital converter with on-chip precisiontrimming

The design and performance of a 12-b charge redistribution analog-to-digital converter (ADC) is described. The architecture is chosen to minimize power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a 1-μm CMOS process. It converts at a 200-kHz rate with a power dissipation of 10 mW