门电路参数对互连线时延影响的仿真研究

文章推广了Wang氏RC梯形电路模型，对互连线阶跃响应上升时间与门电路参数的关系进行了仿真研究，给出了定量结果。门电路参数有输出电阻、输入电阻和电容。     

基于门时延的时间间隔测量系统的实现及其不确定度分析

文章介绍了一种基于门时延的时间间隔测量系统的实现方法,简述了所用芯片的结构和特性;然后给出了时间间隔测量系统的软硬件设计思路。最后对整个测量系统的测量不确定度进行分析,证明了此方式的实现成本低、模块体积小、可靠性高。     

InGaP/InGaAs Pseudomorphic Heterodoped-Channel FETs With a Field Plate and a Reduced Gate Length by Splitting Gate Metal

Depositing gate metal across a step undercut between the Schottky barrier layer and the insulator-like layer is employed to obtain a reduced gate length of 0.4 mum with an additional 0.6-mum field plate from a 1-mum gate window. Most dc and ac characteristics including current density (I_DSS=451mA/mm), transconductance (g_m,max=225mS/mm), breakdown voltages (V_BD(DS)/V _BD(GD)=22/-25.5V), gate-voltage swing (GVS=2.24V), cutoff, and maximum oscillation frequencies (f_t/f_max=17.2/32GHz) are improved as compared to those of a 1-mum gate device without field plate. At a V_DS of 4.0 V, a maximum power added efficiency of 36% with an output power of 13.9 dBm and a power gain of 8.7 dB are obtained at a frequency of 1.8 GHz. The saturated output power and the linear power gain are 316 mW/mm and 13 dB, respectively     

On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment

This paper deals with the performance of a Carbon Nano Tube Field Effect Transistor (CNTFET) in the presence of undeposited CNTs as defects. A simulation-based analysis of delay degradation due to different features (such as chirality and defective CNT distribution) is initially pursued. Two solutions to mitigate the change in delay are proposed; these approaches are based on adjusting the gate width of the CNTFET by lithography (and removing CNTs) as part of the fabrication process. These two methods reduce the average delay and its deviation, respectively. A probabilistic delay analysis is then presented. The performance of the proposed two adjustment methods is evaluated by considering CNT features (such as chirality and defect distribution) deterministically and probabilistically. By deterministic (probabilistic) simulation, the first method reduces on average the delay by 6.968 % (7.811 %) while the deviation is increased (decreased) by 32.444 % (9.788 %). The second method reduces deterministically (probabilistically) on average the deviation by 44.159 % (47.476 %) with 2.166 % (4.409 %) delay reduction.     

门电路延迟时间的Multisim仿真测试方案

介绍了用Multisim仿真软件测试门电路延迟时间的方法，提出了三种测试方案，即将奇数个门首尾相接构成环形振荡电路，用虚拟示波器测试所产生振荡信号的周期，计算门的传输延迟时阔；奇数个门首尾相接构成环形振荡电路，用虚拟示波器测试其中一个门的输入信号、输出信号波形及延迟时间；在一个门的输入端加入矩形脉冲信号，测试一个门的输入信号、输出信号波形及延迟时间。所述方法的创新点是，解决了受示波器上限频率限制实际硬件测试效果不明显的问题，并给出Multisim软件将门的初始输出状态设置为0时，使测试电路不能正常工作的解决方法。     

驱动复杂RLC互连树的逻辑门延时

提出了一个用于估计RL C互连树驱动点导纳的闭端等效π模型,并将其用于驱动复杂RL C互连树的逻辑门延时的估计中.与其他方法相比,它具有结构简单、精度较高的特点     

驱动复杂RLC互连树的逻辑门延时

提出了一个用于估计RLC互连树驱动点导纳的闭端等效π模型,并将其用于驱动复杂RLC互连树的逻辑门延时的估计中.与其他方法相比,它具有结构简单、精度较高的特点.     

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.     

考虑NBTI效应的逻辑门退化延迟模型

基于45 nm PTM模型,采用Hspice对基本逻辑门进行了仿真,并使用Matlab对仿真数据进行了三维延迟曲面拟合。在这些仿真基础上,建立了关于输入信号翻转时间t_i、输出负载电容CL、阈值电压变化量ΔV_th的传播延迟t_p和输出翻转时间t_o的计算模型。采用时延模型对基准测试电路ISCAS85-C17进行了计算,并将计算结果与Hspice仿真数据进行了对比。结果表明,在仿真范围(t_i=0~100 ps,CL=0~2 fF,ΔVth =0~50 mV)内,该时延模型计算值与仿真数据的相对误差在±10%以内。该模型及其计算方法可适用于大规模数字IC的可靠性设计。     

非线性延时模型及逻辑门优化设计

为了解决信号斜率对逻辑门延时的影响,提出一种基于逻辑努力的非线性逻辑门延时模型.模型引入非线性修正因子,该修正因子通过对仿真数据的模拟,由优化算法求得.针对不同的连线负载,提出模型得到的延时与仿真得到的延时误差小于3％.仿真结果表明,在不同的连线负载下,采用该模型优化设计的译码器延时最小,验证了模型的有效性.     

TFT AMLCD像素矩阵电路中栅延迟的模拟研究

建立了ａ－ＳｉＴＦＴＡＭＬＣＤ的等效电路模型,综合考虑栅信号线电阻、栅与源信号线的交叠电容以及ＴＦＴ导电沟道电容构成的ＲＣ（ＲｅｓｉｓｔｉｖｉｔｙＣａｐａｃｉｔａｎｃｅ）常数,模拟计算了栅信号延迟对液晶显示屏尺寸、显示分辨率及栅信号电极材料的依赖关系,为实现器件优化设计提供参考。     

Quality Determination for Gate Delay Fault Tests Considering Three-State Elements

Most industrial digital circuits contain three-state elements besides pure logic gates. This paper presents a gate delay fault simulator for combinational circuits that can handle three-state elements like bus drivers, transmission gates and pulled busses. The well known delay faults--slow-to-rise and slow-to-fall--are considered as well as delayed transitions from isolating signal state high impedance to binary states 0 and 1 and vice versa. The presented parallel delay fault simulator distinguishes between non-robust, robust and hazard free tests and determines the quality of a test. Experimental results for ISCAS85/89 benchmark circuits are presented as well as results for industrial circuits containing three-state elements.     

减少纳米MOS器件栅电流的研究分析

采用Schroedinger-Poisson方程自洽全量子求解法研究了MOS器件不同介质材料和栅结构栅电流,该模型对栅电流中的三维电流成分用行波统一地计算;对二维栅电流成分通过反型层势阱中准束缚态的隧穿率计算。模拟得出栅极电流与实验结果符合。研究结果表明,采用高愚栅介质材料、p-MOSFET或双栅结构对栅电流的减少有明显的作用,这一结果可望对器件性能作出预计并对其研制提供指导。     

Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion

Capacitive crosstalk between adjacent signal wires has significant effect on performance and delay uncertainty of point-to-point on-chip buses in deep submicrometer (DSM) VLSI technologies. We propose a hybrid polarity repeater insertion technique that combines inverting and non-inverting repeater insertion to achieve constant average effective coupling capacitance per wire transition for all possible switching patterns. Theoretical analysis shows the superiority of the proposed method in terms of performance and delay uncertainty compared to conventional and staggered repeater insertion methods. Simulations at the 90-nm node on semi-global METAL5 layer show around 25% reduction in worst case delay and around 86% delay uncertainty minimization compared to standard bus with optimal repeater configuration. The reduction in worst case capacitive coupling reduces peak energy which is a critical factor for thermal regulation and packaging. Isodelay comparisons with standard bus show that the proposed technique achieves considerable reduction in total buffers area, which in turn reduces average energy and peak current. Comparisons with staggered repeater which is one of the simplest and most effective crosstalk reduction techniques in the literature show that hybrid polarity repeater offers higher performance, less delay uncertainty, and reduced sensitivity to repeater placement variation.      

基于门延时的数字TDC电路设计

为了扩大时间数字转换(Time to Digital Converter,TDC)的测量范围并提高其分辨率,确保测量结果的正确有效,提出了一种数字TDC电路的设计方法.采用与工艺无关的环形门延时单元的设计方法,缩小了电路规模,且可以方便地移植到其它系统中.通过Verilog HDL语言对该设计进行了RTL级的描述,最后通过了时序仿真和FPGA验证.该设计方法与现有设计方法相比,使用较少的逻辑资源达到了大量程高精度的测量要求,计数结果正确稳定.     

On Minimizing Delay with Probabilistic Splitting of Traffic Flow in Heterogeneous Wireless Networks

In the paper,we propose a framework to investigate how to effectively perform traffic flow splitting in heterogeneous wireless networks from a queue point.The average packet delay in heterogeneous wireless networks is derived in a probabilistic manner.The basic idea can be understood via treating the integrated heterogeneous wireless networks as different coupled and parallel queuing systems.The integrated network performance can approach that of one queue with maximal the multiplexing gain.For the purpose of illustrating the effectively of our proposed model,the Cellular/WLAN interworking is exploited.To minimize the average delay,a heuristic search algorithm is used to get the optimal probability of splitting traffic flow.Further,a Markov process is applied to evaluate the performance of the proposed scheme and compare with that of selecting the best network to access in terms of packet mean delay and blocking probability.Numerical results illustrate our proposed framework is effective and the flow splitting transmission can obtain more performance gain in heterogeneous wireless networks.     

Network Coding for Overhead Reduction in Delay Tolerant Networks

Employing Network Coding (NC) in routing protocols for Delay Tolerant Networks (DTNs) is a challenging issue during the last years due to its potential beneficial effect on improving relevant critical metrics. This paper proposes an effective NC scheme intended for sparse DTNs comprising nodes of limited storage capacity. The scheme employs a memory management algorithm that makes optimal use of the limited storage capacity and focuses on unicast sessions where source and intermediate nodes combine only packets belonging to the same generation and destined for the same destination node. Upon having received a sufficient number of linearly independent packets resulting in a matrix of full rank, the destination nodes can apply network decoding to retrieve the information intended for them. The proposed scheme is fully distributed since the network nodes make decisions based on information collected solely from their own buffers. Combined either with Epidemic or probabilistic routing protocols, the scheme manages to drastically reduce the overhead created per source packet.     

An Advanced Effective Capacitance Model for Calculating Gate Delay Considering Input Waveform Effect

In deep submicron designs, predicting gate delay time is a noteworthy work for Static Timing Analysis. The effective capacitance Ceff concept is usually used to calculate the gate delay with interconnect loads. Conventionally, the input-signal to the gate is always assumed as a ramp waveform. However, the input signal is also the output of CMOS gates with interconnect loads and not the ramp waveform. Thus the simple assumption as a ramp signal results in significant influence on the delay calculation. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and the interconnect loads, where the nonlinear influence of input waveform is modeled as one part of the effective capacitance for calculating the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.     

On the Influence of Delay Line Uncertainty in THz Time-Domain Spectroscopy

Terahertz time-domain spectroscopy (THz TDS) is a well-known tool for material analysis in the terahertz frequency band. One crucial system component in every time-domain spectrometer is the delay line which is necessary to accomplish the sampling of the electric field over time. Despite the fact that most of the uncertainty sources in TDS have been discussed, the delay line uncertainty has not been considered in detail. We model the impact of delay line uncertainty on the acquired THz TDS data. Interferometric measurements of the delay line precision and THz time-domain data are used to validate the theoretical model.     

Theory Comparison: Uncertainty Reduction, Problematic Integration, Uncertainty Management, and Other Curious Constructs

This paper compares 3 theories examining the role of communication in producing and coping with subjective uncertainty. Uncertainty reduction theory offers axioms and derived theorems that describe communicative and noncommunicative causes and consequences of uncertainty. The narrow scope of the theory and its axiomatic form are both advantageous and disadvantageous. Problematic integration and uncertainty management theories are comparatively broad, and they exhibit an open, web-like structure. The former theory scrutinizes the complex intersection of probability assessments and evaluations of the objects of these assessments, whereas the latter examines the various ways in which people cope with uncertainty, including sometimes attempting to increase it. The paper also compares meanings of "uncertainty" in the 3 theories as well as the roles played by natural language in the communication-uncertainty interface.