CMOS image sensors

In this article, we provide a basic introduction to CMOS image-sensor technology, design and performance limits and present recent developments and future directions in this area. We also discuss image-sensor operation and describe the most popular CMOS image-sensor architectures. We note the main non-idealities that limit CMOS image sensor performance, and specify several key performance measures. One of the most important advantages of CMOS image sensors over CCDs is the ability to integrate sensing with analog and digital processing down to the pixel level. Finally, we focus on recent developments and future research directions that are enabled by pixel-level processing, the applications of which promise to further improve CMOS image sensor performance and broaden their applicability beyond current markets.     

Review of CMOS image sensors

The role of CMOS Image Sensors since their birth around the 1960s, has been changing a lot. Unlike the past, current CMOS Image Sensors are becoming competitive with regard to Charged Couple Device (CCD) technology. They offer many advantages with respect to CCD, such as lower power consumption, lower voltage operation, on-chip functionality and lower cost. Nevertheless, they are still too noisy and less sensitive than CCDs.Noise and sensitivity are the key-factors to compete with industrial and scientific CCDs. It must be pointed out also that there are several kinds of CMOS Image sensors, each of them to satisfy the huge demand in different areas, such as Digital photography, industrial vision, medical and space applications, electrostatic sensing, automotive, instrumentation and 3D vision systems.In the wake of that, a lot of research has been carried out, focusing on problems to be solved such as sensitivity, noise, power consumption, voltage operation, speed imaging and dynamic range. In this paper, CMOS Image Sensors are reviewed, providing information on the latest advances achieved, their applications, the new challenges and their limitations. In conclusion, the State-of-the-art of CMOS Image Sensors.     

CMOS image sensors in ISSCC 2023

<正>In IEEE International Solid-State Circuits Conference(ISSCC) 2023, CMOS process is still the dominating fabrication technology for image sensors, and three-dimensional(3D)wafer-stacked process with Cu–Cu pixel-level connection has been adopted to achieve small pixel size and high integration level. The development of CMOS image sensors(CIS) is still focusing on the trends of high performance and more functionalities,     

CMOS image sensors: State-of-the-art

This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.     

Combined image signal processing for CMOS image sensors

An efficient image signal processing structure is proposed for CMOS image sensors to achieve low area and power consumption. In the proposed structure, the gamma correction block is moved to the front to merge several image signal processings into one block. An efficient compensation scheme is also proposed to reduce the errors caused by the moving of the nonlinear gamma correction. Experimental results show that the proposed structure reduces area and power consumption by 23.8 and 31.1%, respectively.     

CMOS image sensors: electronic camera-on-a-chip

CMOS active pixel sensors (APS) have performance competitive with charge-coupled device (CCD) technology, and offer advantages in on-chip functionality, system power reduction, cost, and miniaturization. This paper discusses the requirements for CMOS image sensors and their historical development, CMOS devices and circuits for pixels, analog signal chain, and on-chip analog-to-digital conversion are reviewed and discussed     

CMOS image sensors for sensor networks

We report on two generations of CMOS image sensors with digital output fabricated in a 0.6 μm CMOS process. The imagers embed an ALOHA MAC interface for unfettered self-timed pixel read-out targeted to energy-aware sensor network applications. Collision on the output is monitored using contention detector circuits. The image sensors present very high dynamic range and ultra-low power operation. This characteristics allow the sensor to operate in different lighting conditions and for years on the sensor network node power budget. Eugenio Culurciello (S’97–M’99) received the Ph.D. degree in Electrical and Computer Engineering in 2004 from Johns Hopkins University, Baltimore, MD. In July 2004 he joined the department of Electrical Engineering at Yale University, where he is currently an assistant professor. He founded and instrumented the E-Lab laboratory in 2004. His research interest is in analog and mixed-mode integrated circuits for biomedical applications, sensors and networks, biological sensors, Silicon on Insulator design and bio-inspired systems. Andreas G. Andreou received his Ph.D. in electrical engineering and computer science in 1986 from Johns Hopkins University. Between 1986 and 1989 he held post-doctoral fellow and associate research scientist positions in the Electrical and Computer engineering department while also a member of the professional staff at the Johns Hopkins Applied Physics Laboratory. Andreou became an assistant professor of Electrical and Computer engineering in 1989, associate professor in 1993 and professor in 1996. He is also a professor of Computer Science and of the Whitaker Biomedical Engineering Institute and director of the Institute’s Fabrication and Lithography Facility in Clark Hall. He is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Between 2001 and 2003 he was the founding director of the ABET accredited undergraduate Computer Engineering program. In 1996 and 1997 he was a visiting professor of the computation and neural systems program at the California Institute of Technology. In 1989 and 1991 he was awarded the R.W. Hart Prize for his work on mixed analog/digital integrated circuits for space applications. He is the recipient of the 1995 and 1997 Myril B. Reed Best Paper Award and the 2000 IEEE Circuits and Systems Society, Darlington Best Paper Award. During the summer of 2001 he was a visiting professor in the department of systems engineering and machine intelligence at Tohoku University. In 2006, Prof. Andreou was elected as an IEEE Fellow and a distinguished lecturer of the IEEE EDS society. Andreou’s research interests include sensors, micropower electronics, heterogeneous microsystems, and information processing in biological systems. He is a co-editor of the IEEE Press book: Low-Voltage/Low-Power Integrated Circuits and Systems, 1998 (translated in Japanese) and the Kluwer Academic Publishers book: Adaptive Resonance Theory Microchips, 1998. He is an associate editor of IEEE Transactions on Circuits and Systems I.     

Passivation issues in active pixel CMOS image sensors

Most of the integrated circuit industry follows a final passivation process which consists of a low temperature passivation layer deposition and a thermal anneal. This two step process is particularly relevant in CMOS imagers where the dark current is a major issue. This work shows that passivation material plays an important role in the device performance. We measured H diffusion through the final silicon nitride layer and we compare these results with the material properties and passivation efficiency.     

CMOS传感器在视频采集系统中的应用

介绍了数字视频采集系统的原理和结构，并从工作原理及结构上比较了两种主要图像传感器的特点。文章详细介绍了一种CMOS传感器及处理芯片的内部结构、特点及其在视频采集、处理等方面的应用。最后给出了以VV6500和STV0680B为核心的视频监控系统实例。     

Latch-up and image crosstalk suppression by internal gettering [in CMOS]

Internal gettering can be used to reduce crosstalk in imagers and latchup susceptibility in CMOS circuits. The internal gettering process forms defects in the bulk of the silicon wafers that are effective recombination sites for minority carriers in the substrate. Experimental and theoretical results are presented for crosstalk reduction obtained in an area imager. The current gain /spl beta/ of the parasitic lateral n-p-n transistors formed in the substrate in CMOS circuits was considerably lower for the internally gettered wafers. The trigger current needed to initiate latch-up in the n-p-n-p structures increased as 1//spl beta/, in accordance with the theory. A Monte Carlo method was developed to calculate the expected transistor current gain. The calculated /spl beta/s are in excellent agreement with the measured values.     

A high dynamic range pixel using lateral overflow integration capacitor and adaptive feedback structure in CMOS image sensors

This letter proposes a novel high dynamic range(HDR) pixel using lateral overflow integration capacitor(LOFIC) and adaptive feedback structure. Through detailed analysis of the voltage feedback mechanism, the conversion gain(CG), full well capacity(FWC) and dynamic range(DR) performances of the feedback LOFIC pixel are analytically expressed. The verification results reveal that the equivalent FWC of the feedback LOFIC pixel is 1.89 times of conventional LOFIC pixel, and the DR extension is 5.5 ...     

A linear stepping PGA used in CMOS image sensors

A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.     

一种应用于CMOS图像传感器中的线性步进PGA设计

A low power linear stepping digital programming gain amplifier （PGA） is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.     

Transversal-readout architecture for CMOS active pixel image sensors

Novel architecture for CMOS active pixel image sensors (APSs), which eliminates the vertically striped fixed pattern noise (FPN), is presented. There are two kinds of FPN for CMOS APSs. One originates from the pixel-to-pixel variation in dark current and source-follower threshold voltage, and the other from the column-to-column variation in column readout structures. The former may become invisible in the future due to process improvements. However, the latter, which results in a vertically striped FPN, is and will be conspicuous without some subtraction because of the correlation in the vertical direction. The pixel consists of a photodiode, a row- and column-reset transistor, a source-follower input transistor, and a column-select transistor instead of the row-select transistor found in conventional CMOS APSs. The column-select transistor is connected to a signal line that runs horizontally instead of vertically. An experimentally fabricated 320/spl times/240-pixel CMOS APS employing the transversal-readout architecture exhibited neither vertically nor horizontally striped FPN. A buried-photodiode device with the transversal-readout architecture is also proposed.     

适用于时间延迟积分CMOS图像传感器的高级数模拟累加器

本文分析并解决了应用于TDI CMOS 图像传感器的模拟累加器的寄生问题。为了抑制寄生问题所引入累加器信噪比的降低,在已有的具有去耦开关的模拟累加器中,采用上级板采样,在积分阶段注入补偿电荷,来补偿无法消除的寄生所带来的影响。并且通过加入校正电路来抑制工艺偏差和器件失配带来的影响。在设计中采用0.18-μm 1P4M工艺,供电电压为3.3V。后仿真结果表明,累加器所能提升的信噪比从17.835dB增加到了21.067dB。此外,累加器的整体线性度达到了99.62%。同时通过对电路进行蒙特卡洛仿真,结果表明校正电路很好的抑制了工艺偏差和器件失配带来的影响。所以,本文提出的结构可用于构建高级数的模拟累加器。     

A Nyquist-rate pixel-level ADC for CMOS image sensors

A multichannel bit-serial (MCBS) analog-to-digital converter (ADC) is presented. The ADC is ideally suited to pixel-level implementation in a CMOS image sensor. The ADC uses successive comparisons to output one bit at a time simultaneously from all pixels. It is implemented using a 1-bit comparator/latch pair per pixel or per group of neighboring pixels, and a digital-to-analog-converter/controller shared by all pixels. The comparator/latch pair operates at very slow speeds and can be implemented using simple robust circuits. The ADCs can be fully tested by applying electrical signals without any optics or light sources. A CMOS 320×256 sensor using the MCBS ADC is described. The chip measures 4.14×5.16 mm². It achieves 10×10 μm² pixel size at 28% fill factor in 0.35 μm CMOS technology. Each 2×2 pixel block shares an ADC. The pixel block circuit comprises 18 transistors. It operates in subthreshold to maximize gain and minimize power consumption. The power consumed by the sensor array is 20 mW at 30 frames/s. The measured integral nonlinearity is 2.3 LSB, and differential nonlinearity is 1.2 LSB at eight bits of resolution. The standard deviation of the gain and offset fixed pattern noise due to the ADC are 0.24 and 0.2%, respectively     

Light guide for pixel crosstalk improvement in deep submicron CMOS image sensor

Light guide, a novel dielectric structure consisting of PE-Oxide and FSG-Oxide, has been developed to reduce crosstalk in 0.18-/spl mu/m CMOS image sensor technology. Due to the difference in refraction index (1.46 for PE-Oxide and 1.435 for FSG-Oxide), major part of the incident light can be totally reflected at the interface of PE-Oxide/FSG-Oxide, as the incidence angle is larger than total reflection angle. With this light guide, the pixel sensing capability can be enhanced and to reduce pixel crosstalk. Small pixels with pitch 3.0-/spl mu/m and 4.0-/spl mu/m have been characterized and examined. In 3.0-/spl mu/m pixel, optical crosstalk achieves 30% reduction for incidence angle of light at 10/spl deg/.     

双CMOS图像传感器的抗晕光图像采集系统设计

为解决CMOS图像传感器采集图像时产生晕光问题,提出一种CMOS图像传感器的抗晕光图像采集系统设计方案.TMS320C6414采用阈值化分割算法,对两路图像数据进行剪裁,汲取各自图像的优点,输出一路比较清晰的图像信息.其效果相当于扩大了CMOS图像传感器的动态范围,从而达到抗晕光的效果.     

3-D optical and electrical simulation for CMOS image sensors

The optical and electrical characteristics of CMOS image sensors, such as readout, saturation, reset, charge-voltage conversion, and crosstalk characteristics, are analyzed by a three-dimensional (3-D) device simulator SPECTRA and a 3-D optical simulator TOCCATA which were developed for the analysis of CCD image sensors. The model of readout operation for a buried photodiode with potential barrier and dip is discussed with consideration of thermal diffusion. The transient simulation is executed for readout and reset operation. A novel calculation method for photodiode saturation condition is proposed. The optical and electronic crosstalk is analyzed individually by ray-tracing and current calculation. It is found that the above methods successfully analyze the optical and electrical characteristics of CMOS image sensors.     

Characterization of crosstalk noise in submicron CMOS integratedcircuits: an experimental view

A way to characterize the crosstalk noise susceptibility for integrated circuits fabrication technologies is presented. A comparison between 0.7- and 0.35-μm technologies shows the increasing importance of crosstalk noise and, therefore, the need to consider this effect at the design level in submicron integrated circuits. An approach to measure the internal crosstalk generated by long metal interconnects based on using an RS latch sensor is proposed. An implementation and experimental measurements for 0.7-μm technology are reported, confirming the very high noise peak values