一种混合信号边界扫描测试系统的设计

IEEE 1149.4的推出为混合信号测试提供了一个标准,推动了混合信号边界扫描测试技术的研究。简要介绍了IEEE 1149.4标准及混合信号测试方法,并根据标准定义的测试结构设计出一种混合信号边界扫描测试系统。经过测试验证,该系统能够对混合信号电路进行互连测试和参数测试,可实现准确的故障诊断,具有一定的实用价值。     

混合信号总线测试实例

混合信号电路(Mixed-signalCircuits)广泛应用于通信、多媒体、工业电子和消费类电子产品中。其测试方法有很多,其中基于边界扫描技术的混合信号测试总线已越来越受欢迎。在定义混合信号测试总线时,要求不仅能够测试桥接故障、开路故障、对模拟元件值进行测试,而且还要能够与IEEE1149.1兼容。为此,IEEE半导体工业协会(SA)标准委员会于1999年6月批准了建立混合信号测试总线标准的1149.4文件。     

IEEE1149.4模拟和混合信号测试总线标准

模拟和混合信号边界扫描标准(IEEE1149.4)是针对电路板级外部分立元件的测试而发展起来的,该标准与IEEE1149.1兼容,另外,在此基础上,IEEE1149.4又增加了两根线,用来控制模拟信号.目前1149.4的标准,不但应用在传统的电路板上,在混合信号集成电路甚至包含混合信号的SoC系统芯片上,都有应用.本文...     

从边界扫描技术协议讨论其发展与应用

边界扫描测试技术作为当前电子测试技术的热点,其应用与发展是令人瞩目的。本文通过对边界扫描技术一系列协议的简单介绍和剖析,讨论了边界扫描技术各个阶段的应用与发展情况,并对边界扫描技术未来的发展给出了一些预测。     

基于边界扫描技术的集成电路测试系统设计与实现

介绍了边界扫描的技术原理,及其在集成电路测试中的具体应用,并给出了一种基于边界扫描技术的板级集成电路测试系统的方案及实现。     

混合信号边界扫描测试系统的设计与实现

分析了混合信号边界扫描测试的工作机制对测试系统的功能需求,实现了符合IEEE1149.4标准的混合信号边界扫描测试系统。仿真和测试实践表明,该测试系统具有对系统级、PCB级和芯片级电路进行简单互连测试、差分测试和参数测试等功能,结构简单、携带方便、工作可靠。     

边界扫描测试技术

边界扫描技术是一种标准化的可测试性设计方法,它提供了对电路板上元件的功能、互连及相互间影响进行测试的一种新方案,极大地方便了系统电路的测试.介绍了边界扫描技术的原理、结构,讨论了边界扫描技术的应用.     

模拟集成电路的边界扫描可测性设计方案

提出了一种基于边界扫描技术的模拟集成电路内建自测试方案。该方案依照IEEE 1149.4边界扫描测试标准, 在添加极少电路元件的基础上, 增加了电路性能测试单元(FTM), 能够充分利用电路系统中已有数模混合资源, 通过控制器内部向被测电路施加激励, 完成模拟集成电路的功能性测试。采用Cyclone II系列芯片EP2C35F672C8实现测试系统设计, 并以模拟集成滤波芯片MAX292为被测核心电路展开实验, 其频率特性的测试结果表明了该测试方案的正确性和系统测试的有效性。     

用下行链路实现远程边界扫描测试

将内部IEEE 1149架构与集成在产品中的通信端口链接起来,供外界使用.     

边界扫描测试的原理及应用

本文简要介绍了边界扫描测试产生的背景，原理，以及应用，最后还阐述了边界扫描在设计时需要注意的问题。     

SOC混合信号测试难题的解决策略

缺乏可控制性和可观察性是SOC嵌入式内核测试电路最难解决的问题.本文提出在SOC嵌入式内核测试电路中引入DFT和BIST方法.介绍了IEEE1149.4混合信号测试总线及其应用特点,讨论运用重配置的DFT方法和测试点插入的DFT方法来增强混合信号系统的可控制性和可观察性.阐述ADC/DAC与PLL两种电路的BIST技术在SOC嵌入式内核测试的应用.为解决SOC混合信号测试难题提供一种有效的方法.     

An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase.The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.     

基于IEEE1149.4的测试方法研究

根据混合信号边界扫描测试的工作机制，提出了符合l149．4标准的测试方法，并用本研究室开发的混合信号边界扫描测试系统进行了测试验证。     

Measurement of digital noise in mixed-signal integrated circuits

This paper proposes a method of measuring the influence of digital noise on analog circuits using wide-band voltage comparators as noise detectors. Noise amplitude and r.m.s voltage are successfully measured by this method. A test chip is fabricated to measure the digital noise influence. From the experimental results, it is shown that the digital noise influence can be considerably reduced by using a differential configuration in analog circuits for mixed-signal IC's. The digital noise influence can be further reduced by lowering the digital supply voltage. These results show that the voltage-comparator-based measuring method is effective in measuring the influence of digital noise on analog circuits     

混合信号集成电路的衬底耦合噪声分析

本文系统分析了混合信号集成电路的衬底噪声耦合的研究进展.简要分析了衬底噪声的基本机理,及其对混合信号电路的影响,在此基础上分析比较了目前已提出的几种主要的衬底耦合噪声模型.通过分析不同类型衬底内的噪声耦合,介绍了一些电路设计中的去耦方法.最后讨论了衬底耦合噪声研究的发展方向.     

混合信号总线测试

文中介绍了使用本研究室开发的混合信号边界扫描测试系统对KLIC实验芯片进行简单互连、扩展互连测试和CLUSTER测试。通过对测试结果的分析表明，IEEE1149．4测试总线在这些测试中是非常成功的，并同时指出了其局限性。     

Computer-aided design considerations for mixed-signal coupling inRF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.