A Software Defined Radio Platform with Direct Conversion: SOPRANO

In this paper, a new software defined radio platform with direct conversionisintroduced.The platform is named SOPRANO, which stands for Software Programmableand Hardware Reconfigurable Architecture for Network.Main features of SOPRANO include a high-level design methodologyfor digital circuits, direct conversion based on six-port technology, andnovel digital signal processingalgorithms for multi-band and multi-mode operation.The first prototype of the SOPRANO platform has been built and was ableto receive M-ary PSK (Phase Shift Keying)and QAM (Quadrature Amplitude Modulation) signals,with two different carrier frequencies at 2.45 GHz and 5.25 GHz,by changing signal-processing software.     

基于FPGA的软件无线电调制器设计与实现

针对数字基带信号的特点和通信系统中对数字信号传输的要求,研究一种基于FPGA的DSP技术和DDS技术的软件无线电调制器的设计方法。在FPGA平台上设计具有ASK,FSK,PSK和QAM调制功能的软件无线电调制器。该系统具有可重复编程和动态重构的优点,使系统易于修改和功能升级,灵活性强。     

卫星常用调相信号自动调制识别算法

针对高阶幅度相移键控（APSK）信号在卫星通信中的应用,提出了一种识别数字调相信号的新方法。在信噪比估计的基础上,利用信号包络的统计特征对MPSK,MQAM,16APSK和32APSK信号进行区分。理论推导和实验仿真验证了该统计特征具有对加性高斯白噪声和滚降系数不敏感的特性。根据鲁棒性较好的四阶循环累积量提出一种新的特征参数Q以实现MPSK和MQAM信号的类内识别。仿真表明,当信噪比达到5dB时,该方法拥有较好的识别率（〉95％）。     

D/A转换在System View环境下的仿真及硬件实现

针对模拟信号在传输介质中优于数字信号,而设计数模转换模块。首先用System View对DAC模块进了仿真。然后设计的D/A转换的硬件电路。通过设计了一个前置的串并转换电路,不仅可以实现8位并行数字信号的D/A转换,还可实现8位串口输入数字信号的D/A转换。在输出端,接入一个有源二阶低通滤波电路,使模拟输出更为平滑。达到了在实际范围内较低波形衰减的目的。     

软件无线电基带处理系统的DSP实现

给出了一种基于DSP技术实现的软件无线电基带处理系统，包括一个DSB模拟调制系统和一个FSK数字调制系统，并对软件无线电在移动通信领域的应用进行了探讨。     

Adaptive digital/RF predistortion using a nonuniform LUT indexing function with built-in dependence on the amplifier nonlinearity

This paper reports on an integrated adaptive digital/RF predistorter using a nonuniform spaced lookup table (LUT) and in-phase/quadrature (I/Q) RF vector multiplier (VM). The LUT contents are directly deduced from the baseband input and output signals of the power amplifier (PA). In addition, a new nonlinear indexing function of the predistortion LUT with built-in dependence on the PA nonlinearity is proposed. This function is made to be robust to the input signal statistics. A comparison of this new indexation method with conventional approaches, namely, power and logarithmic power indexation functions, is carried out. The superiority of the proposed scheme is demonstrated in particular for class-AB amplifiers where the gain of the PA varies over the whole input range of the drive signal. The measured output spectrum of a linearized 90-W peak lateral double-diffused metal-oxide-semiconductor PA reveals a significant reduction of the power emission at the adjacent channels of approximately 15 dB under IS95, single-carrier, and multicarrier wide-band code-division multiple-access signals. The experimental evaluation is carried out using an RF/digital predistorter prototype that mainly includes an envelope detector, a linear I/Q RF VM, field-programmable gate array and digital signal processor, and fast analog/digital and digital/analog converters.     

RF I/Q Downconverter With Gain/Phase Calibration

We propose an RF I/Q downconverter including a calibration procedure to compensate for gain and phase mismatch errors. The indirect compensation technique is based on the use of the local oscillator (LO) signal as reference for error measurements. A number of mismatch parameters are first estimated by an algorithm running in the digital signal processing processor following the analog-to-digital converter and then used to correct the downconverted I/Q signals digitally during normal operation. The downconverter has been designed in 0.13-mum CMOS technology. The analog part of the system for calibration adds a negligible area and power consumption with respect to the front-end building blocks. Test results exhibit an image-rejection ratio IRRges48.8 dB for I/Q phase errors up to 15deg and for LO I/Q amplitude and mixer gain mismatch errors up to 10%     

A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit

A digital channel multiplexer for satellite outdoor unit running at 1 GHz clock frequency is implemented in 65 nm CMOS mixed oxide dual voltage technology. This multiplexer, based on a 1 GS/s digital signal processor (DSP) approach with 500 MHz input and output bandwidth, embeds two 8 bit 1 GS/s analog-digital converters (ADCs) and two 8 bit 1 GS/s digital-analog converter (DACs). It consumes less that 1022 mW at ambient temperature while achieving noise rejection up to 42.5 dB on a single tone, and > 37 dB on modulated satellite channels.     

调制混合滤波器组的宽带模拟信号采样研究

对于超宽带模拟信号,很难用单个模拟数字转换器（ADC）直接进行采样。该文提出了一种新的并行调制混合滤波器组结构用于实现超宽带模拟信号的采样,首先,将每一路宽带模拟输入信号进行余弦调制,并用相同的低通模拟滤波器均匀分割输入信号的带宽;然后,采用相同的ADC将子带信号数字化;各路子带信号通过上采样器后用数字综合滤波器综合得到原宽带模拟输入信号的数字重构。综合滤波器采用总体最小二乘准则下的特征值滤波器设计方法得到。本文所提出的系统结构不需要使用高速的采样保持电路,降低了系统实现的难度,并且设计的系统具有与其它混合滤波器组相近的重构性能。仿真结果表明了本方法的有效性。      

A Disruptive Receiver Architecture Dedicated to Software-Defined Radio

The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable radio architecture accepting all cellular or noncellular standards working in the 0-5-GHz frequency range. Some technical challenges have to be solved in order to address this concept. Working in the digital domain may be a solution but the analog-to-digital conversion cannot be done at Radio Frequencies, at an acceptable resolution and at an acceptable level of power consumption. The idea proposed here was to interface an analog pre-processing circuit between the antenna and a digital signal processor to pre-condition the RF signal. It uses the principle of a fast Fourier transform to carry out basic functions with high accuracy in a low-cost technology like CMOS. This paper presents the design and the behavioral simulations of this analog discrete-time device which gives the hardware flexibility required for a cognitive radio component.     

A VLSI architecture for a high-speed all-digital quadraturemodulator and demodulator for digital radio applications

An all-digital architecture is presented for implementing the front-end signal-processing functions in a quadrature modulator and demodulator for high bit-rate digital radio applications. A pair of CMOS chips has been designed and submitted for fabrication in a 1.25-μm process and is expected to accommodate symbol rates up to 35 MBd. The modulator chip accepts a pair of 8-b in-phase and quadrature data streams and generates a bandlimited IF output with an excess bandwidth factor of 35%. The demodulator chip accepts a digitized IF input signal and generates a pair of filtered in-phase and quadrature baseband signals. The modulator and demodulator chips each incorporate 40-tap multiplierless FIR (finite-impulse response) square-root Nyquist matched filters, and the cascade of the two chips achieves a peak intersymbol interference distortion of -54 dB. The modulator chip can generate any arbitrary signal constellation within a rectangular grid of 256×256 points. Thus, the all-digital implementation results in a generic chip set suitable for a wide variety of high bit-rate digital modem designs using formats such as M-ary PSK and QAM     

Corona Based Optimal Node Deployment Distribution in Wireless Sensor Networks

This paper shows the trade off between different modulation techniques such as multi level quadrature amplitude modulation, multi level phase shift keying, and multi level differential phase shift keying for upgrading direct detection optical orthogonal frequency division multiplexing systems with possible transmission distance up to 15,000 km and total bit rate of 2.56 Tb/s. The 2.56 Tb/s signal is generated by multiplexing 64 OFDM signals with 40 Gb/s for each OFDM. Variations of optical signal to noise ratio (OSNR), signal to noise ratio (SNR), and bit error rate (BER) are studied with the variations of transmission distance. Maximum radio frequency power spectrum, and output electrical power after decoder are measured for different multi level modulation techniques with carrier frequency. It is observed that multi level QAM has presented better performance than multi level PSK and finally multi level DPSK in optical OFDM systems. Maximum output power after decoder is enhanced with both 32-PSK, and 64-QAM. Quadrature signal amplitude level at encoder is upgraded with 64-QAM. It is noticed that OSNR, SNR, and BER are improved using 4-QAM OFDM system than either QPSK or 4-DPSK.     

一种基于FPGA的自动功率控制电路设计与实现

由于导航数字接收机模拟前端的差异性及其采用的A/D转换电路不同,导致数字中频信号功率变化范围较大,且量化后的数字信号有效比特位数有较大差异。为了优化后续的基带数字信号处理过程,提出了一种基于FPGA的自动功率控制电路的实现方案。该电路通过可变点数的求平均运算,统计出信号的直流分量,然后将去直流后的信号进行功率估计,最后由功率反馈调整单元进行增益调整,从而保证输出信号的功率基本稳定。     

基于决策论的数字调制信号识别方法

以决策论为基础提出了一种改进的数字调制信号识别方法,该方法仅需4个相对简单的特征参数,就能识别2ASK、4ASK、2FSK、4FSK、2PSK、4PSK和16QAM这7种数字调制信号。仿真结果表明,该方法复杂度较低,识别正确率有较大提高,尤其对于2ASK、4ASK、MPSK/MFSK及16QAM的识别,在信噪比较低的情况下,具有较好的识别效果。     

声表面波射频识别系统的FMCW信号源设计

频率调制连续波(FMCW)的产生(即FMCW信号源)是声表面波射频识别系统频域采样阅读器的重要组成部分。为了满足扫频速度、带宽和线性度等要求,采用直接数字频率合成器(DDS)与锁相环(PLL)混频,并结合IQ调制的方式设计了超高频FMCW信号源。实际制作了信号源电路,DDS芯片输出I、Q两路正交信号,并分别以差分形式传输至IQ调制芯片进行上变频。测试了DDS输出信号的差分、正交特性,分别对信号源产生的单频信号和扫频信号进行了测试。最后搭建系统对声表面波标签进行测试。测试结果表明信号源设计的有效性。     

Toward Wide-Band High-Resolution Analog-to-Digital Converters Using Hybrid Filter Bank Architecture

The paper presents the problem of design and simulation of a high-speed wide-band high-resolution analog-to-digital (ADC) converter working in a bandpass scenario. Such converters play a crucial role in software-defined radio and in cognitive radio technology. One way to circumvent the limits of today’s ADC technologies is to split the analog input signal into multiple components and then sample them with ADCs in parallel. The two main split approaches, time interleaved and frequency splitting, can be modeled using a filter bank paradigm, where each of these two architectures requires a specific analysis for its design. In this research, the frequency splitting approach was implemented with the use of a hybrid filter bank ADC, which requires an output digital filter bank perfectly matched to the input analog filter bank. To achieve this end, an analog transfer function, together with an assumption of strictly band-limited input signal, has been used to design the digital filter bank so far. In contrast, the author proposes dropping the band-limit assumption and shows that the out-of-band input signal has to be taken into account when designing a hybrid filter bank.     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13 μm CMOS

A single-chip, dual-band transceiver for CDMA2000 is presented. The design supporting the North American cellular and PCS bands features a complete zero-IF receiver, a direct-conversion transmitter and two fully integrated synthesizers with VCOs. The analog receiver front-end comprises two self-matched wideband LNAs, a highly linear demodulator and a third-order baseband filter. In a test version I/Q ADCs and a digital front-end (DFE) to provide channel and matched filtering are included to demonstrate the performance of a fully integrated analog/digital line-up. Measured maximum SNR values of 23 dB and 25 dB for PCS and Cell bands, respectively, are achieved. The transmitter comprises baseband buffers and filters, an I/Q-modulator and separate output drivers for each band. An analog gain control (AGC) for realization of a dynamic range is implemented and a maximum output power of at a total CDG4 urban current of 34 mA is achieved for the PCS band. Measured ACPR1 and values are and 0.998 for the Cell band and and 0.995 for the PCS band, respectively. The chip is fabricated in a 0.13 RF-CMOS process, occupies a die size of 8.4 and operates with a 2.5 V supply.     

Frequency-Agile Dual-Band Direct Conversion Receiver for Cognitive Radio Systems

A frequency-agile dual-band direct conversion receiver is proposed and experimentally validated for cognitive radio system applications. Two types of tunable receiver architectures are presented and analyzed in this work; one structure relying on a tunable bandpass filter, and a second system based on a varactor—based tunable six-port demodulator, with the latter showing better sensitivity and dynamic range. In order to demodulate phase-shift-keying modulated signals at multiple operating frequencies at a high bit rate of 40 Mb/s, the receiver is designed using a wideband power detector in connection with a high-speed quad comparator. An experimental prototype and a complete measurement test bench have been realized in order to obtain the bit error rate performance of the receiver in a more realistic application environment. In summary, the proposed electronically tunable system allows for an operation in multiband frequency ranges including global system for mobile communications cellular networks (1900 MHz) and IEEE802.11 a/b/g applications (2.4 and 5.8 GHz).      

用于生物医学成像的多通道流水线数字化电路设计

针对生物医学成像中前端读出电路多通道以及要求高速数字化的特点,设计了一个16通道的流水线数字化电路.整个电路由模拟多路选择器、单端转差分电路、8-bit 25Ms/s 1.5bit/stage流水线ADC以及数据输出模块组成.模数转换和数据输出在两相邻时间窗口内采用流水线方式进行.电路采用TSMC 0.18μm mixed signalCMOS工艺实现.电路仿真结果表明,流水线ADC的DNL为-0.62/0.67LSB,INL为-0.39/0.72LSB,SNR为45.99dB,ENOB为6.03bit,该电路能够在两个相邻时间窗口内完成16通道的信号数字化并输出,满足系统设计要求.