MESFET肖特基势垒结参数提取及I-V曲线拟合

运用双指数函数模型方法分析了影响 MESFET的 Ti Pt Au-Ga As肖特基势垒结特性的各种因素及各因素间的关系 ,编制了 MESFET肖特基势垒结结参数提取和 I-V曲线拟合软件 ,实现了通过栅源正向 I-V实验数据提取反映肖特基势垒结特性的六个结参数和得到相应结参数下的理论数据 ,与实验数据吻合良好。分析了影响肖特基势垒结 I-V曲线分布的因素 ,提出了进行器件特性、参数稳定性与可靠性研究和定量分析 MESFET肖特基势垒结质量的新方法     

用于砷化镓单片集成的肖特基势垒

本文阐述了用于GaAs单片集成的Ti—Au系肖特基势垒的有关特性。指出了实现既要有1微米栅长的几何图形,又要有良好电学特性的肖特基势垒的制作条件。采用栅区深腐蚀法和盐酸浸泡法,改善了肖特基势垒特性。针对高温下结退化问题,测量了Ti—Au势垒的正向特性随温度变化的数据,分析了势垒劣化的机理。提出了减小势垒退化应采取的制作方法。     

栅条状和蜂窝状结构结势垒肖特基整流器（JBSR）性能对比

栅条状和蜂窝状平面结构的结势垒肖特基整流管（JBSR）的不同之处在于其沟道有效面积的大小不同。从这两种平面结构的结势垒肖特基整流管（JBSR）的工艺和电学特性来看,适当的增大JBSR器件的沟道有效面积,可使JBSR器件的击穿电压得到提高。蜂窝状平面结构JBSR器件的沟道有效面积较栅条状器件的小,开启电压低,但反向耐压不如栅条状平面结构JBSR器件,这可能是因为蜂窝状器件的P+区的缺陷较于栅条状结构器件的多,同样器件的I-V特性也与结构参数密切相关。     

高低沟道结构的GaAs双栅MESFET

<正>1971年Turner等人提出了在源漏之间设立两个独立的肖特基势垒栅,这种双栅GaAsMESFET由于它具有增益高、稳定性好、信号调制能力强等优点,因此,近来发展较快,在一些领域获得广泛的应用.     

等离子体刻蚀凹栅槽影响AlGaN/GaN HEMT栅电流的机理

对等离子体干法刻蚀形成的凹栅槽结构AlGaN/GaN HEMTs肖特基电流增加的机理进行了研究.实验表明,凹栅槽结构AIGaN/GaN HEMTs肖特基栅电流增加一个数量级以上,击穿电压有一定程度的下降.利用AFM和XPS的方法分析AlGaN表面,等离子体干法刻蚀增加了AlGaN表面粗糙度,甚至出现部分尖峰状突起,增大了栅金属与AlGaN的接触面积;另一方面,等离子体轰击使AlGaN表面出现一定量的N空位,相当于栅金属与AlGaN接触界面处出现n型掺杂层,使肖特基结的隧道效应加强,降低了肖特基势垒.由此表明,AlGaN表面粗糙度的增加以及一定量的N空位出现是引起栅电流急剧增大的根本原因.     

高温正向栅电流下Ti/Pt/Au栅SiC MESFET的栅退化机理

SiC MESFET器件的性能强烈依赖于栅肖特基结的特性,而栅肖特基接触的稳定性直接影响其可靠性.针对SiC MESFET器件在微波频率的应用中射频过驱动导致高栅电流密度的现象,设计了两种栅极大电流的条件,观察栅肖特基接触和器件特性的变化,并通过对试验数据的分析,确定了栅的寄生并联电阻的缓慢退化是导致栅肖特基结和器件特性退化,甚至器件烧毁失效的主要原因.     

大束流离子注入形成CoSi2/Si肖特基结电学特性

文中研究了使用大束流金属离子注入形成的CoSi2/Si肖特基结的特性。肖特基结由离子注入和快速热退火两步工艺形成。Co离子注入剂量为3×1017ion/cm2,注入电压25kV。快速热退火温度为850°C,时间为1min。应用I-V和C-V测量进行参数提取。I-V分析得到势垒高度约为0.64eV,理想因子为1.11,C-V分析得到势垒为0.72eV。最后依据实验结果对工艺提出了改进意见。     

等离子体刻蚀凹栅槽影响AlGaN/GaN HEMT栅电流的机理

对等离子体干法刻蚀形成的凹栅槽结构AlGaN/GaN HEMTs肖特基电流增加的机理进行了研究.实验表明,凹栅槽结构AIGaN/GaN HEMTs肖特基栅电流增加一个数量级以上,击穿电压有一定程度的下降.利用AFM和XPS的方法分析AlGaN表面,等离子体干法刻蚀增加了AlGaN表面粗糙度,甚至出现部分尖峰状突起,增大了栅金属与AlGaN的接触面积;另一方面,等离子体轰击使AlGaN表面出现一定量的N空位,相当于栅金属与AlGaN接触界面处出现n型掺杂层,使肖特基结的隧道效应加强,降低了肖特基势垒.由此表明,AlGaN表面粗糙度的增加以及一定量的N空位出现是引起栅电流急剧增大的根本原因.     

GaAs MESFET单片集成电路工艺研究

用缓冲场效应晶体管逻辑(BFL)电路,研究了GaAs MES FET单片集成电路的工艺.为提高单片电路的集成度,给出了设计平面器件最小欧姆接触长度的直读曲线.对磷酸系腐蚀液的工艺特性进行了研究,并与其他几种常用的腐蚀液进行了比较.采用盐酸浸泡法结合栅区深腐蚀技术,明显地改善了肖特基势垒结的特性.利用俄歇能谱仪对Au-Ti-GaAs肖特基势垒结的热退化失效进行了分析,并提出了改善措施.已制出管芯平均传输时延小于100ps的GaAs单片集成门电路.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

Optically-controlled ion-implanted GaAs MESFET characteristic withopaque gate

An analytical modelling has been carried out for an ion-implanted GaAs MESFET having a Schottky gate opaque to incident radiation. The radiation is absorbed in the device through the spacings of source, gate, and drain unlike the other model where gate is transparent/semitransparent. Continuity equations have been solved for the excess carriers generated in the neutral active region, the extended gate depletion region and the depletion region of active (n) and substrate (p) junction. The photovoltage across the channel and the p-layer junction and that across the Schottky junction due to generation in the arc region of the gate depletion layer are the two important controlling parameters. The I-V characteristics and the transconductance of the device have been evaluated and discussed     

GaAs MESFET/PHEMT大信号建模

大信号精确模型的建立是微波单片集成电路设计和研制的基础,在分析传统建模方法的基础上,对传统的Cold FET测量技术和寄生元件参数提取提出了改进方法,大栅宽器件引入了脉冲I-V曲线的测试方法,改进了EEFET/EEHEMT模型的I-V模型和Q-V模型.利用在片测试技术与建模软件相结合,建立了新的二维电荷模型,给出了建模实例和验证结果.     

基于Pspice的RTD等效模型及其应用电路研究

简要介绍了RTD(共振隧穿二极管)的微分负阻特性及其等效电路,通过对实际AlAs/InxGa1-xAs/GaAs双势垒共振隧穿结构I-V曲线拟合,得出RTD的Pspice等效电路模型参数。采用Pspice软件建立了RTD的等效电路模型,并对其微分负阻特性进行了仿真,仿真结果与测试结果基本吻合。利用所建立的模型,对RTD的基本应用电路:反相器、非门、与非门和或非门进行了仿真模拟。结果表明,该类电路能够正确实现其逻辑功能。最后,对基于RTD的振荡电路进行了仿真,仿真频率与实际测试频率处于同一数量级。由于实测电路寄生参数如串联电阻、电容等的影响,仿真结果与测试结果稍有出入。     

Electrical current instability at gate breakdown in GaAs MESFET

The gate burnout (irreversible breakdown) of GaAs MESFET has been studied using two-dimensional (2-D) numerical simulation and experimental measurements of 10 ns pulsed gate-drain I-V characteristics, it is shown, that at some critical level of gate avalanche current the gate current instability appears. The instability results in formation of the negative differential conductivity (NDC) region on the S-shape gate-drain I-V characteristic, spatial instability of avalanche current and formation of high density current filaments. At some critical length of n⁺-contact regions a spatial instability results in spontaneous formation of multiple spatial-periodic filaments     

Frequency-dependent characteristics of an ion-implanted GaAs MESFETwith opaque gate under illumination

Commercial metal-semiconductor-field-effect transistors (MESFET's) have opaque gate. We present here the frequency-dependent characteristics of an ion-implanted GaAs MESFET with opaque gate under illumination. The incident light enters the device through the gate-source and gate-drain spacings. Two photovoltages are developed: one across the Schottky junction due to generation in the side walls of the depletion layer below the gate and the other across the channel-substrate junction due to generation in the channel-substrate depletion region. The frequency dependence of the two photovoltages along with channel charge, drain-source current, transconductance and channel conductance of the device have been studied analytically and compared with the published theoretical results. For the first time, a commercially available GaAs optically illuminated field-effect transistor (OPFET) has been analyzed for frequency dependent characteristics instead of the transparent/semitransparent gate OPFET     

Performance of GaAs JFET at a cryogenic temperature for application to readout circuit of high-impedance detectors

A GaAs junction field effect transistor (JFET) is a promising candidate for the cryogenic electronics of high-impedance sensitive photoconductors because of its low-noise at low frequencies. This GaAs JFET has advantages compared with other type of FETs, such as no kink phenomena or hysteresis in its current-voltage (I-V) characteristics, small gate leakage currents, and minute capacitance. We report on the noise spectra and leakage current of a SONY n-type GaAs FET in a high-impedance configuration where the gate terminal was surrounded by high-impedance devices at a cryogenic temperature, i.e., 4.2 K. In the high-impedance configuration, we obtained a low noise level and low leakage current of 0.5 /spl mu/V/Hz/sup 1/2/ at 1 Hz and 4.6/spl times/10/sup -19/ A. This result implies that the GaAs JFET is suitable for cryogenic readout electronics. We also discuss the source of the random telegraph signal and the 1/f noise in the GaAs JFET at cryogenic temperatures.     

肖特基栅共振隧穿三极管(SGRTT)的器件模拟

使用Atlas软件模拟了肖特基栅共振隧穿三极管。通过改变发射极长度、栅极金属和上层AlAs势垒的距离以及靠近AlAs势垒的GaAs层浓度,得到器件耗尽区边界以及所对应的I-V特性,由此分析和解释了器件结构参数对器件特性的影响,最后对器件在电路中的应用予以说明。     

Determination of energetic distribution of interface states betweengate metal and semiconductor in sub-micron devices from current-voltagecharacteristics

Density and energetic distributions of interface states between metal-semiconductor rectifying contacts in sub-micron GaAs MESFET and AlGaAs/InGaAs pseudomorphic high electron mobility transistors (HEMT's) have been studied. Electrical properties of the interface states between gate metal and semiconductor in sub-micron devices depend on growth technique, associated processing parameters and surface states on III-V semiconductors. Correlation between nonideal current-voltage (I-V) characteristics and interface states has been established through the bias dependence of ideality factor. Ideality factor determined from I-V characteristics of MESFET and HEMT increases with bias and then decreases after reaching a maximum. A theoretical model based on nonequilibrium approach has been used to determine the density of interface states and their energetic distribution from ideality factor. Essentially, Fermi level shifts with applied bias and Schottky barrier height changes due to trapping and detrapping of electrons by the interface states, and from these changes, density of interface states and their energetic distributions have been determined     

根据IV曲线形态定性判断PN结性能的一种简易方法

利用MATLAB灵活丰富的绘图功能,在半对数坐标下画出了PN结的IV曲线。根据其形态,可以对PN结的性能作出定性判断。逼近该曲线所需的直线段越多,说明该PN结的性能与理想状态相距越远。这种方法不仅适用于同质PN结,也适用异质PN结和肖特基势垒二极管。