Exploiting low complex digital predistortion to improve wideband nonlinear satellite downlinks

With the increasing demand for higher data rate, increasing throughput requires wider bandwidth. Due to the nonlinear effect of power amplifier, severe nonlinear distortion effects will appear onboard satellite. Digital predistortion (DPD) scheme is usually employed to compensate for the distortions and memory effects introduced by traveling wave tube amplifier (TWTA) and output multiplexing filter (OMUX). In conventional predistorter, the signal loss of band‐limited feedback signal output through OMUX is usually ignored. Actually, it will affect the linear effect of TWTA. In order to solve the problem as to improve wideband nonlinear satellite downlink, this paper introduces a novel spectral extrapolation method based on deep neural network to recover the band‐limited feedback signal. On this basis, an advanced orthogonal matching pursuit algorithm is adopted in the nonlinear TWTA model construction to further reduce the DPD complexity. The proposed setup effectively compensates the distortions and is well suited for systems that generate data bits on satellites.     

Multi-Lookup Table FPGA Implementation of an Adaptive Digital Predistorter for Linearizing RF Power Amplifiers With Memory Effects

This paper presents a hardware implementation of a digital predistorter (DPD) for linearizing RF power amplifiers (PAs) for wideband applications. The proposed predistortion linearizer is based on a nonlinear auto-regressive moving average (NARMA) structure, which can be derived from the NARMA PA behavioral model and then mapped into a set of scalable lookup tables (LUTs). The linearizer takes advantage of its recursive nature to relax the LUT count needed to compensate memory effects in PAs. Experimental support is provided by the implementation of the proposed NARMA DPD in a field-programmable gate-array device to linearize a 170-W peak power PA, validating the recursive DPD NARMA structure for W-CDMA signals and flexible transmission bandwidth scenarios. To the best of the authors' knowledge, it is the first time that a recursive structure is experimentally validated for DPD purposes. In addition to the results on PA efficiency and linearity, this paper addresses many practical implementation issues related to the use of FPGA in DPD applications, giving an original insight on actual prototyping scenarios. Finally, this study discusses the possibility of further enhancing the overall efficiency by degrading the PA operation mode, provided that DPD may be unavoidable due to the impact of memory effects.     

基于偏最小二乘的低复杂度数字预失真

在宽带场景下,传统的数字预失真(DPD)模型需要更高的阶次和更多的系数来校正功率放大器(PA)强非线性和记忆效应,这就会导致极高的计算复杂度和解算系数时的病态问题.文章围绕复杂DPD模型参数辨识和低复杂度DPD算法实现展开深入研究,提出了一种新的基于偏最小二乘(PLS)的低复杂度DPD方法.所提方法根据PA的前逆输入输...     

宽带Chrip信号激励下功放数字预失真补偿

功率放大器(power amplifiers, PAs)会对输入的宽带线性调频信号(linear frequency modulated, LFM)引入幅度失真和相位失真,这将导致接收机脉冲压缩处理后的输出信号主瓣展宽,旁瓣电平抬高,从而恶化雷达距离分辨率甚至产生虚假目标。文中提出采用有限冲击响应滤波器(finite impulse response, FIR)模型对宽带LFM信号激励下的功放进行行为建模和数字预失真(digital predistortion, DPD)补偿。利用宽带测试平台对500 MHz 瞬时带宽LFM信号激励下峰值功率15 W 的S波段功放进行验证。实验结果表明,浅饱和和深饱和情况下FIR模型都能准确建模功放的失真特性,浅饱和情况下DPD能够补偿幅度失真和相位失真,而深饱和情况下只能补偿相位失真,经过DPD补偿脉冲压缩后的峰值旁瓣电平都明显降低。     

基于RPE算法的记忆多项式数字预失真研究

数字预失真(DPD)是一种能有效地补偿功率放大器(PA)非线性失真的技术.基于记忆多项式预失真的非直接学习结构(ILA),采用RPE(Recursive Predlotion Error)算法构造了非线性PA的自适应预失真模型,推导了该算法在预失真系统中的递推公式,给出了计算机仿真结果,在相同参数下,通过与RLS算法在系统中的仿真结果进行比较,证明了该算法对消除PA非线性失真的有效性.     

Complexity-reduced Volterra series model for power amplifier digital predistortion

This paper expounds a complexity-reduced Volterra series model for radio frequency power amplifier (PA) behavioral modeling and digital predistortion (DPD). An analysis was conducted, which took into account the memory effect mechanisms of the PA. This led to a closed-form expression that relates the memoryless behavior of the PA to the finite impulse response feedback filter, which approximates the memory effects’ behavior. The analysis resulted in a complexity-reduced Volterra series model which allows for a substantial reduction in the requirements for digital signal processors and the time needed to construct and implement the DPD in a real-time environment. The proposed model was validated as a behavioral model and a DPD using two different PA architectures, employing two different transistor technologies, driven by both 20 MHz 1001 wideband code division multiple access and long term evolution signals. The results obtained demonstrate the excellent modeling and linearization capability of the complexity-reduced Volterra series model.     

一种基于维度加权盲K近邻算法的数字预失真技术

传统的数字预失真(DPD)模型通常在所有的输入信号功率上采用单一多项式模型和单一记忆深度对功率放大器(PA)进行线性化矫正。然而,功率放大器在不同的功率水平下会呈现出不同的非线性特性,并产生不同的记忆效应。针对这一问题,该文提出一种基于维度加权盲K近邻(KNN)算法的数字预失真模型,所提模型根据功放当前输入信号以及记忆输入信号的幅度进行维度加权的KNN分类,组成维度加权盲KNN记忆多项式(WKMP)模型,并为每一类输入信号序列建立子模型。所提方法用Doherty功率放大器进行实验验证,使用带宽为30 MHz、频点为2.2 GHz的3载波长期演进(LTE)信号作为输入,反馈端使用122.88 MHz的采样率进行采样。实验结果表明,所提维度加权盲KNN分类方法与记忆多项式(MP)模型结合时,功放正向建模效果和数字预失真效果均超过了广义记忆多项式(GMP)模型,并远超记忆多项式模型的效果,实验结果验证了所提模型的优良性能。     

Dynamic Behavioral Modeling of Power Amplifiers Using ANFIS-Based Hammerstein

This letter presents a novel structure for the dynamic behavioral modeling of radio frequency power amplifiers (RF PAs) with ANFIS-based Hammerstein model for memory effects. The model is an adaptive neuro-fuzzy inference system (ANFIS) followed by a finite impulse response (FIR) filter. A hybrid learning algorithm is adopted to identify the parameters of the ANFIS. The parameters of the FIR filter are estimated by a straightforward least-squares method. The input and output signals of the PA excited with a three-carrier WCDMA signal were sampled for the model identification and validation in a test bench. Experimental results in the frequency and the time domains show that the proposed model was able to give an accurate approximation to characterize the wideband RF PAs.     

Piecewise Pre-Equalized Linearization of the Wireless Transmitter With a Doherty Amplifier

This paper describes a predistorter (PD) based on piecewise pre-equalizers for use in multichannel wideband applications. The predistortion linearizer consists of piecewise pre-equalizers along with a look-up-table-based digital PD that together compensate for nonlinearities, as well as memory effects of power amplifiers (PAs). It takes advantage of multiple finite-impulse-response filters that significantly reduce the complexity when compared to memory polynomial methods. The proposed method was also compared with the conventional Hammerstein structure. A 300-W peak envelope power Doherty PA was first modeled by measured time-based samples in order to verify the adjacent channel power ratio (ACPR) performance in simulation using a multitone and single wideband code-division multiple-access (W-CDMA) carrier. Furthermore, the experimental results applying two W-CDMA carriers verify that the proposed method provided similar improvement to that of the memory polynomial approach. The experimental results verified the complexity reduction and superior ACPR performance over the conventional Hammerstein structure.     

Weighted Polynomial Digital Predistortion for Low Memory Effect Doherty Power Amplifier

We have proposed a simple and effective weighted polynomial digital predistortion algorithm, which consists of weighting, least square polynomial fit, and de-weighting. The weighting factor is introduced to describe the signal distribution statistics and high harmonic generation at a high power region to improve accuracy of the error function. A low memory linear Doherty power amplifier (PA) has been realized with two 90-W peak envelope power LDMOSFETs using memory effect reduction techniques, and the proposed algorithm has been applied to the PA. For the forward-link wideband code division multiple access 3FA signal, the adjacent channel leakage ratio performance at 5-MHz offset is -56 dBc with power-added efficiency of 20.78% at an average power of 40 dBm. The proposed weighting polynomial algorithm provides a significantly reduced error power and superior convergence behavior with improved linearization capability than the conventional polynomial. Moreover, the low memory Doherty amplifier could be linearized for a wideband signal using the simple algorithm without any memory effect compensation     

A least-squares/Newton method for digital predistortion of wideband signals

Power amplifiers (PAs) are essential in communication systems, but are inherently nonlinear. To achieve linearity with good efficiency, PA linearization is necessary. Digital baseband predistortion is a highly cost-effective way to linearize PAs, but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications, such as wideband code-division multiple access, PA memory effects can no longer be ignored. Therefore, in order to achieve good linearization performance, the predistorter needs to also have memory structure. In this paper, we propose a new model for the wideband predistorter and a least-squares(LS)/Newton algorithm to estimate the model parameters. Performance of the LS/Newton algorithm is studied through computer simulations. Good linearization performance is achieved by using the new model in an experimental testbed.     

基于调制域分析的功放线性化测量验证

针对目前功率放大器(Power Amplifier,PA)线性化测量验证方案需要较多的软硬件资源且测试效率低的问题,提出了一种适用于卫星通信领域的PA线性化测量与验证方法.该方法基于信号的调制域分析,首先信源端生成循环I/Q数据,然后经调制域分析仪进行信号采集后,由所提算法进行非线性特性提取,最后进行数字预失真(Digital Pre-distortion,DPD)算法验证.从仿真及测试结果来看,该测量验证方法对P A的非线性建模准确,最小二乘算法DP D效果明显.误差矢量幅度由11.17％降至5.49％,邻信道功率比由-31.75 dBc降低至-42.43 dBc,较好地补偿了PA的非线性特性.测量验证方案平台硬件资源简易,能够便捷获取高阶调制信号激励下的PA非线性测量以及有潜力验证各类DP D算法.     

A robust digital baseband predistorter constructed using memory polynomials

Power amplifiers (PAs) are inherently nonlinear devices and are used in virtually all communications systems. Digital baseband predistortion is a highly cost-effective way to linearize PAs, but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored, and memoryless predistortion has limited effectiveness. In this paper, instead of focusing on a particular PA model and building a corresponding predistorter, we focus directly on the predistorter structure. In particular, we propose a memory polynomial model for the predistorter and implement it using an indirect learning architecture. Linearization performance is demonstrated on a three-carrier WCDMA signal.     

非均匀采样率并发双频数字预失真技术

5G通信的高速发展对发射机支持多模式多频带并发有了新的需求.考虑非均匀采样率并发双频场景下发射机的线性化方案,针对低采样率频段失真频谱超过采样带宽,从而恶化建模精度这一问题,提出一种混叠消除的并发双频数字预失真(DPD)方案.该方案通过在高采样率下构造模型基函数,然后通过低通滤波器来滤除超出采样带宽的频谱分量,再降采样...     

Frequency-Selective Predistortion Linearization of RF Power Amplifiers

This paper presents a frequency-selective RF vector predistortion linearization system for RF multicarrier power amplifiers (PAs) affected by strong differential memory effects. Differential memory effects can be revealed in two-tone experiment by the divergence for increasing tone-spacing of the vector Volterra coefficients associated with the lower and upper intermodulations tones. Using large-signal vector measurement with a large-signal network analyzer, a class-AB LDMOS RF PA is demonstrated to exhibit a strong differential memory effect for modulation bandwidth above 0.3 MHz. New frequency-selective RF and baseband predistortion linearization algorithms are proposed to separately address the linearization requirements of the interband and inband intermodulation products of both the lower and upper sidebands. Theoretical verification of the algorithms are demonstrated with Matlab simulations using a Volterra/Wiener PA model with memory effects. The baseband linearization algorithm is next implemented in a field-programmable gate array and experimentally investigated for the linearization of the class-AB LDMOS PA for two carrier wideband code-division multiple-access signals. The ability of the algorithm to selectively linearize the two interband and four inband intermodulation products is demonstrated. Adjacent channel leakage ratio of up to 45 dBc for inband and interband are demonstrated experimentally at twice the typical fractional bandwidth.     

A Fully Recurrent Neural Network-Based Model for Predicting Spectral Regrowth of 3G Handset Power Amplifiers With Memory Effects

Efficient and accurate behavioral models of power amplifiers (PAs) with memory effects are important for predicting the distortions generated by PAs in 3G handsets. Conventional recurrent neural network (RNN) has been applied for RF PAs, but its capability to model PAs with memory effects has not been investigated. In this letter, we propose a new fully RNN with Gamma tapped-delay lines suitable for modeling the dynamic behavior of 3G PAs with memory effects. After being trained with wideband code division multiple access (W-CDMA) (3GPP Uplink) signals, the proposed model is validated with not only W-CDMA but also high-speed downlink packet access (3GPP Uplink) signals with higher peak-to-average ratios (PARs), which demonstrates the generality of the model. The comparisons with previous RNN models show that the proposed model offers improved performance in predicting spectral regrowth by reducing errors by 1.7-4dB     

基于数/模混合预失真技术的功放线性化北大核心CSCD

随着移动通信信号带宽的增加,传统功率放大器数字预失真线性化技术越来越受到采样率的限制。为了使线性化效果更好,文中提出了一种数字预失真和模拟预失真相结合的混合预失真器,利用模拟预失真宽带宽的特点和数字预失真线性化能力强的优势,把模拟预失真和数字预失真融合在一起,共同补偿功放的非线性。由于受实验设备采样率的限制,文中采用了带宽为60 MHz的5 G NR信号对一个中心频率为3.5 GHz的射频功放进行实验验证。实验结果表明:提出的混合预失真器不仅优于单独的数字预失真器和模拟预失真器的非线性矫正性能,而且还能改善数字预失真因采样率限制无法改善的带外互调失真。     

基于改进型径向基函数神经网络的功放线性化

提出了一种基于改进型径向基函数神经网络(MRBFNN)的数字预失真线性化模型,用于更为精确地矫正宽带射频功率放大器的动态非线性。该神经网络模型的输入层使用传统的延时抽头以补偿功放的线性记忆效应,同时对每个抽头进行级数展开用于补偿功放的非线性记忆效应,从而更好地抑制功放的动态非线性失真。文中使用WCDMA 三载波信号对一个460MHz 的Doherty 功率放大器进行数字预失真线性化实验。实验结果表明,与传统数字预失真线性化模型相比,基于改进型径向基神经网络的数字预失真线性化模型能更好地抑制宽带功放动态非线性引起的带外频谱再生,其三阶互调(IMD3)失真最多可以抑制23dB,大大提高了功放的线性度,验证了所提出的数字预失真线性化模型的有效性。     

A Method to Reduce Sampling Rate of the ADC in Feedback Channel for Wideband Digital Predistortion

This paper presents a new digital predistortion (DPD) solution for wideband signals with low feedback sampling rate. To reduce the minimum sampling rate of the analog-to-digital converter (ADC) for wideband digital predistortion, the proposed method uses a bandpass filter to form a narrowband signal before the ADC. Then, a deconvolution operation is performed to recover the original wideband signal from the ADC samples. The proposed method is evaluated with an international mobile telecommunication-advanced signal with 100 MHz bandwidth. The simulation results show that the recovered signal of the proposed method closely approximates to the original signal in the passband of the filter, and the mean square error of the deconvolution decreases as the signal-to-noise ratio increases. The proposed algorithm can reduce the sampling rate of the ADC from 1105.92 million samples per second (MSPS) to 368.64 MSPS, and improve the adjacent channel power ratio more than 20 dB, which is merely 5.6 dB less than the conventional DPD with 1105.92 MSPS sampling rate.     

一种基于LS/SVD的基带预失真算法

自适应基带预失真技术是用于补偿高功率放大器非线性失真的一种有效技术。早期对预失真的研究大多局限于无记忆非线性,但对于OFDM等宽带应用,放大器的记忆效应明显。介绍了一种基于最小二乘奇异值分解(LS/SVD)的自适应算法来实现有记忆非线性功放的自适应基带预失真。仿真结果表明,该方案用于正交频分复用(OFDM)系统中能有效抑制带外频谱扩散,减小带内失真,实现有记忆非线性功率放大器的自适应预失真。