An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits

Leakage power reduction is extremely important in the design of scaled CMOS logic circuits. The dominant leakage components of such circuits are the subthreshold leakage and the thin-oxide gate leakage. This paper describes an efficient leakage reduction method that considers both these components, and is based on the selective insertion of control points. The selection is based on the leakage reduction potential and the delay insensitivity of the candidate gates. Simulations on the ISCAS85 benchmark circuits show that this method results in$sim67hbox%$leakage reduction with no speed degradation when control points are added to 93% of the gates compared to the leakage of the baseline circuit whose inputs have been subjected to the minimum leakage vector.     

Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits

Sleep transistor (ST) insertion is a valuable leakage reduction technique in circuit standby mode. Fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improve circuit noise margins. In this paper, we introduce a novel two-phase FGSTI technique which consists of ST placement and ST sizing. These two phases are formally modeled using mixed integer linear programming (MILP) models. When the circuit timing relaxation is not large enough to assign ST everywhere, leakage feedback (LF) gates, which are used to avoid floating states, induce large area and dynamic power overhead. An extended multi-object ST placement model is further proposed to reduce the leakage current and the LF gate number simultaneously. Finally, heuristic algorithms are developed to speed up the ST placement phase. Our experimental results on the ISCAS'85 benchmarks reveal that: 1) the two-phase FGSTI technique achieves better results than the simultaneous ST placement and sizing method; 2) when the circuit timing relaxation varies from 0% to 5%, the multi-object ST placement model can achieve on average 4 $times$-9 $times$ LF gate number reduction, while the leakage difference is only about 8% of original circuit leakage; 3) our heuristic algorithm is 1000 $times$ faster than the MILP method within an acceptable loss of accuracy.      

Leakage Power Characteristics of Dynamic Circuits in Nanometer CMOS Technologies

Temperature-dependent subthreshold and gate-oxide leakage power characteristics of domino logic circuits under the influence of process parameter variations are evaluated in this paper. Preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low-leakage circuit design guidelines are presented based on the results. Significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in deeply scaled nanometer CMOS technologies. Contrary to the previously published techniques, a charged dynamic-node voltage state with low inputs is preferred for reducing the total leakage power consumption in the most widely used types of single- and dual-threshold voltage domino gates, particularly at low die temperatures. Furthermore, leakage power savings provided by the dual-threshold voltage domino logic circuit techniques based on input gating are all together reduced due to the significance of gate dielectric tunneling in sub-45-nm CMOS technologies.     

Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits

In this paper, the impact of thermal effects on low-power repeater insertion methodology is studied. An analytical methodology for thermal-aware repeater insertion that includes the electrothermal coupling between power, delay, and temperature is presented, and simulation results with global interconnect repeaters are discussed for 90- and 65-nm technology. Simulation results show that the proposed thermal-aware methodology can save 17.5% more power consumed by the repeaters compared to a thermal-unaware methodology for a given allowed delay penalty. In addition, the proposed methodology also results in a lower chip temperature, and thus, extra leakage power savings from other logic blocks.     

Resistive Power in CMOS Circuits

Interconnect resistance dissipates a portion of the total transient power in CMOS circuits. Conduction losses increase with larger interconnect resistance. It is shown in this paper that these losses do not add to the total power dissipation of a CMOS circuit through I ² R losses. Interconnect resistance can, however, increase the short-circuit power of both the driver and load gates.     

Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits

Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to radiation-induced single-event-upsets (SEUs). Redundancy insertion has been adopted to provide the circuit with additional transient error resiliency. However, its applicability and efficiency are limited by the tight design constraints and budgets. In this paper, we present an intelligent “constraint-aware robustness insertion” methodology. By selectively protecting sequential elements in static CMOS digital circuits, it is able to maximally improve the SEU tolerance while keeping the incurred design overhead within acceptable range. Our technique consists of three major components. The first one is a configurable hardening sequential cell design that serves as the basic building block of the framework; the second one is a robustness calibration technique that evaluates the relative error tolerance of all sequential elements and provides guidelines to the redundancy insertion; the third one is an optimization algorithm that searches for the optimal protection scheme under given design constraints and budgets. Simulation results show that the intelligent robustness insertion reduced the error rate by 46% with zero timing penalty and 10% area increase. Furthermore, by exploring the tradeoffs between reliability and design overhead, we also demonstrate the proposed technique can help achieve high reliability improvement while keeping the design overhead within acceptable range.      

纳米级CMOS电路的漏电流及其降低技术

随着CMOS工艺的进一步发展,漏电流在深亚微米CMOS电路的功耗中变得越来越重要.因此,分析和建模漏电流的各种不同组成部分对降低漏电流功耗非常重要,特别是在低功耗应用中.本文分析了纳米级CMOS电路的各种漏电流组成机制并提出了相应的降低技术.     

Power consumption estimation in CMOS VLSI chips

Power consumption from logic circuits, interconnections, clock distribution, on chip memories, and off chip driving in CMOS VLSI is estimated. Estimation methods are demonstrated and verified. An estimate tool is created. Power consumption distribution between interconnections, clock distribution, logic gates, memories, and off chip driving are analyzed by examples. Comparisons are done between cell library, gate array, and full custom design. Also comparisons between static and dynamic logic are given. Results show that the power consumption of all interconnections and off chip driving can be up to 20% and 65% of the total power consumption respectively. Compared to cell library design, gate array designed chips consume about 10% more power, and power reduction in full custom designed chips could be 15%     

Power Filter Insertion Loss Evaluated in Operational-Type Circuits

Insertion losses of several different manufacturers' 100-ampere power filters were measured in the frequency range 100 Hz to 2 MHz and at a range of power current loads utilizing a newly developed current injection probe. The measurements were made using a technique which, in compliance with IEEE measurement standards, provides a constant voltage source in a filter-in filter-out measurement circuit, where source and load impedance parameters are known. Theoretically derived curves for the power filters installed in circuits with complex source and load impedance are compared to measured curves. Theoretically derived curves for current or voltage attenuation are also compared to insertion loss curves. Significant departures from the MIL-STD-220A specification curves were obtained using this new current injection probe measurement method. Strong saturation effects were found with several of the filters. Wide passband excursions were obtained as predicted by the theoretical treatment. The new measurement technique is described in terms of its relation to IEEE standard definitions of insertion loss. A discussion is given of present and proposed methods in relationship to what is felt is the most useful means of describing a filter's operational characteristics.     

Behavioral Testability Insertion for Datapath/Controller Circuits

A method for test synthesis in the behavioral domain is described.The approach is based on the notion of adding a test behavior to the normal-mode design behavior. This testbehavior describes the behavior of the design in test mode. Thenormal-mode design behavior and test-mode test behavior are combinedand then synthesized by any general-purpose synthesis system toproduce a testable design with inserted BIST structures. The testbehavior is derived from the design behavior using testabilityanalysis based on metrics that quantify the testability of signalsand variables embedded within behaviors. The insertion method iscombined with a behavioral test scheme thatintegrates a) the design controller and test controller, b) testingof the entire datapath and controller. Examples show that when thetestability insertion procedure is used to modify a behavior beforesynthesis, the resulting synthesized physical implementation isindeed more easily tested than an implementation synthesized directlyfrom the original behavior.     

Optimization of device area and overall delay for CMOS VLSI designs

This paper addresses specific design tradeoffs that should be considered relative to CMOS VLSI designs using gate-array, semi-custom, or full-custom implementations. The main focus is on design optimization for speed and device area and on meeting the on-chip load drive requirements using one- and two-dimensional expansion techniques. Detailed comparisons are made between the effectiveness of the various design options in their ability to yield a specific performance within speed and/or area constraints while driving on-chip loads with and without geometrical constraints. These comparisons result in a number of design curves that cover the range of full CMOS custom design, for which two-dimensional scaling can be optimally utilized, to those cases involving semi-custom and gate-array designs for which geometric constraints exist (fixed height cells or fixed device sizes). A figure of merit is defined that relates speed and area to each specific circuit implementation, indicating that it can be used to make an effective comparison between overall performance and design option. It is finally suggested that a chip layout approach can be adopted that is useful for implementing any of the design options discussed.     

Quantifying Error in Dynamic Power Estimation of CMOS Circuits

Conventional power estimation techniques are prone to many sources of error. With increasing dominance of coupling capacitances, capacitive coupling potentially contributes significantly to power consumption in the deep sub-micron regimes. We analyze potential sources of inaccuracy in power estimation, focusing on those due to coupling. Our results suggest that traditional power estimates can be off by as much as 50%.This research was supported in part by the MARCO Gi- gascale Silicon Research Center and Cadence Design Systems, Inc.     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

Configurable CMOS multiplier/divider circuits for analog VLSI

The design of five simple CMOS opamp based multipler/divider circuits is presented. Each two opamp and six MOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applications of the new circuits in analog signal processing and neural networks are discussed. The multiplier/divider circuits are all insensitive to MOS intrinsic parasitic capacitances. They do, however, exhibit different sensitivities to opamp finite unity-gain bandwidth. These sensitivities may be mitigated using the configurability property of the circuits. Finally experimental results are provided to support some of the theoretical claims.     

An Integrated CAD Methodology for Yield Enhancement of VLSI CMOS Circuits Including Statistical Device Variations

In this paper a novel CAD methodology for yield enhancement of VLSI CMOS circuits including random device variations is presented. The methodology is based on a preliminary characterization of the technological process by means of specific test chips for accurate mismatch modeling. To this purpose, a very accurate position-dependent parameter mismatch model has been formulated and extracted. Finally a CAD tool implementing this model has been developed. The tool is fully integrated in an environment of existing commercial tools and it has been experimented in the STMicroelectronics Flash Memory CAD Group.As an example of application, a bandgap reference circuit has been considered and the results obtained from simulations have been compared with experimental data. Furthermore, the methodology has been applied to the read path of a complex Flash Memory produced by STMicroelectronics, consisting of about 16,000 MOSFETs. Measurements of electrical performances have confirmed the validity of the methodology, and the accuracy of both the mismatch model and the simulation flow.     

Wire Topology Optimization for Low Power CMOS

An increasing fraction of dynamic power consumption can be attributed to switched interconnect capacitances. Non-uniform wire spacing depending on activity had shown promising power reductions for on-chip buses. In this paper, a new and fast routing optimization methodology based on non-uniform spacing is proposed for entire circuits. No area investment is required, since whitespace remaining after detailed routing is exploited. The proposed methodology has been implemented and tapped into an industry-proven design flow. Wire power reductions of up to 9.55% for modern multiprocessor benchmarks with tight area constraints are demonstrated, twice as much as approaches that do not take switching activities into account. Timing is not adversely affected, and the yield limit is slightly improved.      

计算机控制技术在电力电子电路中的应用

从电力电子电路数字化控制的要求出友，对分别由单片机、数字信号处理器(DSP)以及微型计算机等为主构成的电力电子电路的计算机控制系统进行了详细介绍和比较分析，指出了电力电子电路新型控制技术的发展方向。     

Power/Ground Network Optimization Considering Decap Leakage Currents

In this brief, the authors take a first look at the leakage effects of decaps in power/ground (P/G) grid optimization. Through the use of an approximate leakage current model, it is revealed that simple usage of the leakage model in traditional optimization methods cannot help in reducing noises on P/G grids, and it even hurts power consumption due to overadded decaps. Therefore, it is necessary to develop an efficient method to budget decaps when leakage effect is considered. Here, a new two-stage approach to solve this problem is proposed. Experimental results demonstrate the effectiveness of our new method     

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

There is one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines. The trigger voltages of LVTSCR devices are lowered to the snapback-breakdown voltages of short-channel NMOS and PMOS devices. This complementary-LVTSCR ESD protection circuit offers four different discharging paths to one-by-one bypass the four modes of ESD stresses at the pad, so it can effectively avoid unexpected ESD damage on internal circuits. Experimental results show that it provides excellent ESD protection capability in a smaller layout area as compared to the conventional CMOS ESD protection circuit. The device characteristics under a high-temperature environment of up to 150/spl deg/C are also experimentally investigated to guarantee the safety of this proposed ESD protection circuit.