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1.
A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is
proposed for MIMO-OFDM WLAN 802.11n. Compared with a conventional MIMO-OFDM implementation, (in which as many FFT/IFFT processors
as the number of transmit/receive antennas is used), the proposed architecture (using hardware sharing among multiple data
sequences) reduces hardware complexity without sacrificing system throughput. Further, the proposed architecture can support
1–4 input data sequences with sequence lengths of 64 or 128, as needed. The FFT/IFFT processor is synthesized using TSMC 0.18 um
CMOS technology and saves 25% area compared to a conventional implementation approach using radix-23 algorithm. The proposed FFT/IFFT processor can be configured to improve power efficiency according to the number of input
data sequences and the sequence length. The processor consumes 38 mW at 75 MHz for one input sequence with 64-point length;
it consumes 87 mW at 75 MHz for four input sequences with length 128-point and can be efficiently used for IEEE 802.11n WLAN
standard.
相似文献
Paul AmpaduEmail: |
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《Circuits and Systems II: Express Briefs, IEEE Transactions on》2008,55(12):1234-1238
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In this paper, we present 64/128/256/512‐point inverse fast Fourier transform (IFFT)/FFT processor for single‐user and multi‐user multiple‐input multiple‐output orthogonal frequency‐division multiplexing based IEEE 802.11ac wireless local area network transceiver. The multi‐mode processor is developed by an eight‐parallel mixed‐radix architecture to efficiently produce full reconfigurability for all multi‐user combinations. The proposed design not only supports the operation of IFFT/FFT for 1–8 different data streams operated by different users in case of downlink transmission, but also, it provides different throughput rates to meet IEEE 802.11ac requirements at the minimum possible clock frequency. Moreover, less power is needed in our design compared with traditional software approach. The design is carefully optimized to operate by the minimum wordlengths that fulfill the performance and complexity specifications. The processor is designed and implemented on Xilinx Vertix‐5 field programmable gate array technology. Although the maximum clock frequency is 377.84 MHz, the processor is clocked by the operating sampling rate to further reduce the power consumption. At the operation clock rate of 160 MHz, our proposed processor can calculate 512‐point FFT with up to eight independent data sequences within 3.2~μs meeting IEEE 802.11ac standard requirements. Copyright © 2015 John Wiley & Sons, Ltd. 相似文献
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设计了一种应用于802.11a的64点FFT/IFFT处理器.采用单蝶形4路并行结构,提出了4路并行无冲突地址产生方法,有效地提高了吞吐率,完成64点FFT/IFFT运算只需63个时钟周期.提出的RAM双乒乓结构实现了对输入和输出均为连续数据流的缓存处理.不仅能实现64点FFT和IFFT,而且位宽可以根据系统任意配置.为了提高数据运算的精度,设计采用了块浮点算法,实现了精度与资源的折中.16位位宽时,在HJTC 0.18μmCMOS工艺下综合,内核面积为:0.626 7 mm2,芯片面积为:1.35 mm×1.27 mm,最高工作频率可达300 MHz,功耗为126.17 mW. 相似文献
5.
基于Good—Thomas映射算法和ISE快速傅里叶变换IP核,设计了一种易于FPGA实现的24点离散傅里叶变换,所设计的24点DFF模块采用流水线结构,主要由3个8点FFT模块和1个3点DFT模块级联而成。并且两级运算之间不需要旋转因子,整个DFF模块仅仅需要14个实数乘法器,布局布线后仿真工作时钟频率可达200MHz。首先根据Good—Thomas算法将并行的24路输入信号分成3组,每组8路信号,并进行并/串转换,得到3路串行信号;其次。将3路串行信号分别输入至3个FFrIP核模块进行8点FFT运算;然后,将上述3个FFrIP核模块同一时刻输出的3路信号进行3点DFF变换;最后,将得到的3路并行输出信号分别进行串/并转换,得到24路DFF输出信号。此外,设计的24点DFT结构还具有很好的扩展性,通过修改FFTIP核变换点数参数便可实现长度N=3×2^N点DFT。 相似文献
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In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency‐division multiplexing ultra‐wideband systems. The proposed 128‐point FFT processor employs both a modified radix‐24 algorithm and a radix‐23 algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure‐sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 µm CMOS technology with a supply voltage of 1.8 V. The hardware‐ efficient 128‐point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128‐point mixed‐radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128‐point FFT architectures. 相似文献
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A 64-point Fourier transform chip for high-speed wireless LAN application using OFDM 总被引:1,自引:0,他引:1
In this paper, we present a novel fixed-point 16-bit word-width 64-point FFT/IFFT processor developed primarily for the application in an OFDM-based IEEE 802.11a wireless LAN baseband processor. The 64-point FFT is realized by decomposing it into a two-dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplications compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift-and-add operations. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The proposed 64-point FFT/IFFT processor has been fabricated and tested successfully using our in-house 0.25-/spl mu/m BiCMOS technology. The core area of this chip is 6.8 mm/sup 2/. The average dynamic power consumption is 41 mW at 20 MHz operating frequency and 1.8 V supply voltage. The processor completes one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 64-point FFT computation in 23 cycles. These features show that though it has been developed primarily for application in the IEEE 802.11a standard, it can be used for any application that requires fast operation as well as low power consumption. 相似文献
8.
基亏DSP的多路音/视频采集处理系统设计 总被引:1,自引:0,他引:1
采用TI公司的TMS320DM642型数字媒体数字信号处理器(DSP)设计多路音/视频采集处理系统,实现实时处理4路模拟视频和音频输入、1路模拟/数字视频和1路模拟音频信号输出的功能,该系统可适应PAL/NTSC标准复合视频CVBS或分量视频Y/C格式的模拟信号和标准麦克风或立体声音频模拟输入,具有PAL/NTSC标准S端子或数字RGB模拟/数字信号输出和标准立体声音频模拟输出。并给出软/硬件设计原理和电路。 相似文献
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J. Mathew K. Maharatna B. R. Jose H. Rahaman D. K. Pradhan 《Circuits, Systems, and Signal Processing》2011,30(4):871-882
An optimal implementation of 128-Pt FFT/IFFT for low power IEEE 802.15.3a WPAN using pseudo-parallel datapath structure is
presented, where the 128-Pt FFT is devolved into 8-Pt and 16-Pt FFTs and then once again by devolving the 16-Pt FFT into 4×4
and 2×8. We analyze 128-Pt FFT/IFFT architecture for various pseudo-parallel 8-Pt and 16-Pt FFTs and an optimum datapath architecture
is explored. It is suggested that there exists an optimum degree of parallelism for the given algorithm. The analysis demonstrated
that with a modest increase in area one can achieve significant reduction in power. The proposed architectures complete one
parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-point
FFT computation in less than 312.5 ns and thereby meet the standard specification. The relative merits and demerits of these
architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of each
of the architectures with a different number of data paths at block level is described. We found that from power perspective
the architecture with eight datapaths is optimum. The core power consumption with optimum case is 60.6 MW which is only less
than half of the latest reported 128-point FFT design in 0.18u technology. Furthermore, a Single Event Upset (SEU) tolerant
scheme for registers is also explored. The SEU tolerant scheme will not affect the performance, however, there is an increase
power consumption of about 42 percent. Apart from the low power consumption, the advantages of the proposed architectures
include reduced hardware complexity, regular data flow and simple counter based control. 相似文献
10.
V. Kitsakis K. Nakos D. Reisis N. Vlassopoulos 《Journal of Signal Processing Systems》2018,90(11):1593-1607
The current paper introduces an efficient technique for parallel data addressing in FFT architectures performing in-place computations. The novel addressing organization provides parallel load and store of the data involved in radix-r butterfly computations and leads to an efficient architecture when r is a power of 2. The addressing scheme is based on a permutation of the FFT data, which leads to the improvement of the address generating circuit and the butterfly processor control. Moreover, the proposed technique is suitable for mixed radix applications, especially for radixes that are powers of 2 and straightforward continuous flow implementation. The paper presents the technique and the resulting FFT architecture and shows the advantages of the architecture compared to hitherto published results. The implementations on a Xilinx FPGA Virtex-7 VC707 of the in-place radix-8 FFT architectures with input sizes 64 and 512 complex points validate the results. 相似文献
11.
Lin Y.-W. Lee C.-Y. 《IEEE transactions on circuits and systems. I, Regular papers》2007,54(4):807-815
In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mum single-poly and eight-metal CMOS process. The core area is 660times2142 mum2 , including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mus meeting IEEE 802.11n standard requirements 相似文献
12.
A 1-GS/s FFT/IFFT processor for UWB applications 总被引:1,自引:0,他引:1
Yu-Wei Lin Hsuan-Yu Liu Chen-Yi Lee 《Solid-State Circuits, IEEE Journal of》2005,40(8):1726-1735
In this paper, we present a novel 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed pipelined FFT architecture, called mixed-radix multipath delay feedback (MRMDF), can provide a higher throughput rate by using the multidata-path scheme. Furthermore, the hardware costs of memory and complex multipliers in MRMDF are only 38.9% and 44.8% of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for the UWB system has been designed and fabricated using 0.18-/spl mu/m single-poly and six-metal CMOS process with a core area of 1.76/spl times/1.76 mm/sup 2/, including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 Gsample/s while it consumes 175 mW. Power dissipation is 77.6 mW when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 Msample/s. 相似文献
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Yuan Chen Yu-Wei Lin Yu-Chi Tsao Chen-Yi Lee 《Solid-State Circuits, IEEE Journal of》2008,43(5):1260-1273
This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-24 FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FFT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 times1.88 mm2 . The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner. 相似文献
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Junha Im Misuk Cho Yongmin Jung Yunho Jung Jaeseok Kim 《Journal of Signal Processing Systems》2012,68(1):19-30
This paper presents an energy-efficient design and the implementation results of a high speed two transmitter—two receiver
multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN baseband processor. The proposed
processor includes a bit-parallel processing physical layer convergence procedure (PLCP) processor which lowers system clock
frequency. A cost-efficient MIMO spatial multiplexing (SM) symbol detector is also proposed in a physical medium dependent
(PMD) processor. The proposed symbol detection algorithm is based on a sorted QR decomposition (SQRD) scheme followed by a
maximum-likelihood (ML) test. The proposed algorithm shows enhanced performance compared to the conventional algorithms such
as SQRD and ordered successive interference cancellation (OSIC) algorithms. The proposed baseband processor supports a maximum
data rate of 130 Mbps at a 40 MHz operation frequency. The power consumptions of the PLCP processor are 27 mW and 93 mW for
TX and RX modes, respectively, which are reduced by 70% compared with that of a common bit-serial architecture. The complexity
of the symbol detector in the PMD processor is reduced by 18% compared with that of the conventional hardware architecture. 相似文献
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A design space exploration methodology of 1-D FFT processor is proposed to find the best hardware architecture in a quantitative way during early design. The methodology includes architecture candidate collection, coarse-grained architecture selection, and circuit level design optimizations. We show how to select a better architecture from candidates including different architectures (SDF, SDC, MDF, MDC and memory-based) with different degree of parallelism at different radices. The sub-level designs, including designs of rotator and data scaling module, are introduced for further optimizations. As a proof of concept, an FFT processor for 4G, WLAN and future 5G is designed supporting 16-4096 and 12-2400 point FFTs. Memory-based architecture with 16-datapath mixed-radix butterfly unit is selected to satisfy the demands for 1GS/s (4096) throughput. The synthesis result based on 65nm technology shows that the silicon cost and power consumption are 1.46mm2 and 68.64mW respectively. The proposed processor has better normalized throughput per area unit and normalized FFTs per energy unit than the state of the art available designs. 相似文献