Architectural Synthesis of Computational Engines for Subband Adaptive Filtering

Architectural synthesis of low-power computational engines (hardware accelerators) for a subband-based adaptive filtering algorithm is presented. The full-band least mean square (LMS) adaptive filtering algorithm, widely used in various applications, is confronted by two problems, viz., slow convergence when the input correlation matrix is ill-conditioned, and increased computational complexity for applications involving use of large adaptive filter orders. Both of these problems can be overcome by the use of a subband-based normalized LMS (NLMS) adaptive filtering algorithm. Since this algorithm is not amenable to pipelining, delayed coefficient adaptation in the NLMS updation is used, which provides the required delays for pipelining. However, the convergence speed of this subband-based delayed NLMS (DNLMS) algorithm degrades with increase in the adaptation delay. We first present a pipelined subband DNLMS adaptive filtering architecture with minimal adaptation delay for any given sampling rate. The architecture is synthesized by using a number of function preserving transformations on the signal flow graph (SFG) representation of the subband DNLMS algorithm. With the use of carry-save arithmetic, the pipelined architecture can support high sampling rates limited only by the delay of two full adders and a 2-to-1 multiplexer. We then extend this synthesis methodology to synthesize a pipelined subband DNLMS architecture whose power dissipation meets a specified budget. This low-power architecture exploits the parallelism in the subband DNLMS algorithm to meet the required computational throughput. The architecture exhibits a novel tradeoff between algorithmic performance (convergence speed) and power dissipation. Finally, we incorporate configurability for filter order, sample period, power reduction factor, number of subbands and decimation/interpolation factor in the low-power architecture, thus resulting in a low-power subband computational engine for adaptive filtering.     

A real-time, low-power implementation for high-resolution eigenvalue-based spectrum sensing

In this paper, a novel multiple antenna, high-resolution eigenvalue-based spectrum sensing algorithm based on the FFT of the received signal is introduced. The proposed platform overcomes the SNR wall problem in the conventional energy detection (ED) algorithm, enabling the detection of the weak signals at ?10 dB SNR. Moreover, the utilization of FFT for the input signal channelization provides a simple, low-power design for a high-resolution spectrum sensing regime. A real-time, low-area, and low-power VLSI architecture is also developed for the algorithm, which is implemented in a 0.18 μm CMOS technology. The implemented design is the first eigenvalue-based detection (EBD) architecture proposed to-date capable of detecting weak signals at ?10 dB. Despite having more algorithmic complexity in comparison to the ED, the proposed EBD architecture shows no significant increase in the core area and the power consumption, due to the FFT utilization for the input signal channelization. The proposed design occupies a total area of 3.4 mm² and dissipates 78 mW for a 40 MHz sensing bandwidth consisting of 32 sub-channels.     

Fourier-Based Feature Extraction for Classification of EEG Signals Using EEG Rhythms

In this paper, we propose a method for the analysis and classification of electroencephalogram (EEG) signals using EEG rhythms. The EEG rhythms capture the nonlinear complex dynamic behavior of the brain system and the nonstationary nature of the EEG signals. This method analyzes common frequency components in multichannel EEG recordings, using the filter bank signal processing. The mean frequency (MF) and RMS bandwidth of the signal are estimated by applying Fourier-transform-based filter bank processing on the EEG rhythms, which we refer intrinsic band functions, inherently present in the EEG signals. The MF and RMS bandwidth estimates, for the different classes (e.g., ictal and seizure-free, open eyes and closed eyes, inter-ictal and ictal, healthy volunteers and epileptic patients, inter-ictal epileptogenic and opposite to epileptogenic zone) of EEG recordings, are statistically different and hence used to distinguish and classify the two classes of signals using a least-squares support vector machine classifier. Experimental results, with 100 % classification accuracy, on a real-world EEG signals database analysis illustrate the effectiveness of the proposed method for EEG signal classification.     

Speed, power, area, and latency tradeoffs in adaptive FIR filteringfor PRML read channels

In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed and latency remain as the main performance criteria for the target application. The proposed parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 premultiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed, and power comparisons with other low-power implementation options are also shown. The proposed filter has been fabricated using a 0.18-μm L-effective CMOS technology and operates at 550 MSamples/s. Trading off filter latency to improve speed is also discussed     

A 900 MHz low power LC-VCO with improved phase noise performance

In this paper, we present the design and development of a low-power LC-VCO with improved phase noise performance by implementing a new capacitor divider varactor configuration and a 2nd order notch filter. We propose a new time-weighted approach to model the effective capacitance experienced by the oscillating signal over the oscillation period. The modeled effective capacitance is used in the calculation of the oscillation frequency, which agrees well with the simulation results. Two VCOs are designed and fabricated in TSMC 0.18 μm technology. The oscillation frequency is tunable from 759 to 910 MHz with a tuning range of 18%. At 900 MHz carrier, the measured phase noise is ?126.1 dBc/Hz at 1 MHz frequency offset with 4.5 mW power consumption.     

VLSI implementation of a new LMS-based algorithm for noise removal in ECG signal

Least mean square (LMS)-based adaptive filters are widely deployed for removing artefacts in electrocardiogram (ECG) due to less number of computations. But they posses high mean square error (MSE) under noisy environment. The transform domain variable step-size LMS algorithm reduces the MSE at the cost of computational complexity. In this paper, a variable step-size delayed LMS adaptive filter is used to remove the artefacts from the ECG signal for improved feature extraction. The dedicated digital Signal processors provide fast processing, but they are not flexible. By using field programmable gate arrays, the pipelined architectures can be used to enhance the system performance. The pipelined architecture can enhance the operation efficiency of the adaptive filter and save the power consumption. This technique provides high signal-to-noise ratio and low MSE with reduced computational complexity; hence, it is a useful method for monitoring patients with heart-related problem.     

Algorithm-based low-power and high-performance multimedia signalprocessing

Low power and high performance are the two most important criteria for many signal-processing system designs, particularly in real-time multimedia applications. There have been many approaches to achieve these two design goals at many different implementation levels ranging from very-large-scale-integration fabrication technology to system design. We review the works that have been done at various levels and focus on the algorithm-based approaches for low-power and high-performance design of signal processing systems. We present the concept of multirate computing that originates from filterbank design, then show how to employ it along with the other algorithmic methods to develop low-power and high-performance signal processing systems. The proposed multirate design methodology is systematic and applicable to many problems. We demonstrate that multirate computing is a powerful tool at the algorithmic level that enables designers to achieve either significant power reduction or high throughput depending on their choice. Design examples on basic multimedia processing blocks such as filtering, source coding, and channel coding are given. A digital signal-processing engine that is an adaptive reconfigurable architecture is also derived from the common features of our approach. Such an architecture forms a new generation of high-performance embedded signal processor based on the adaptive computing model. The goal of this paper is to demonstrate the flexibility and effectiveness of algorithm-based approaches and to show that the multirate approach is an effective and systematic design methodology to achieve low-power and high throughput signal processing at the algorithmic and architectural level     

A UWB-IR Transmitter With Digitally Controlled Pulse Generator

A novel transmitter for ultra-wideband (UWB) impulse radio has been developed. The proposed architecture enables low-power operation, simple design, and accurate pulse-shape generation. The phase and amplitude of the pulse are controlled separately and digitally to generate a desired pulse shape. This digital control method also contributes to the low-power transmission and eliminates the need for a filter. The transmitter is fabricated using a 0.18-mum CMOS process. The core chip size is only 0.40 mm². From experimental measurements, it was found that the generated signal satisfied the FCC spectrum mask, and the average power dissipation was only 29.7 mW at A 2.2-V supply voltage. Therefore, the developed UWB transmitter generates accurate pulses with low power consumption and simple design architecture     

Low-Power Analog Integrated Circuits for Wireless ECG Acquisition Systems

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.     

Approximate Time-Variable Coherence Analysis of Multichannel Signals

We present a new method for signal extraction from noisy multichannel epileptic seizure onset EEG signals. These signals are non-stationary which makes time-invariant filtering unsuitable. The new method assumes a signal model and performs denoising by filtering the signal of each channel using a time-variable filter which is an estimate of the Wiener filter. The approximate Wiener filters are obtained using the time-frequency coherence functions between all channel pairs, and a fix-point algorithm. We estimate the coherence functions using the multiple window method, after which the fix-point algorithm is applied. Simulations indicate that this method improves upon its restriction to assumed stationary signals for realistically non-stationary data, in terms of mean square error, and we show that it can also be used for time-frequency representation of noisy multichannel signals. The method was applied to two epileptic seizure onset signals, and it turned out that the most informative output of the method are the filters themselves studied in the time-frequency domain. They seem to reveal hidden features of the epileptic signal which are otherwise invisible. This algorithm can be used as preprocessing for seizure onset EEG signals prior to time-frequency representation and manual or algorithmic pattern classification.     

All-digital A/D converter TAD with high-resolution and low-power for sensor/RF digitization

For achieving both high resolution and low power of a sensor/RF interface, time-domain processing using full-digital circuits, which deals with only two voltage levels (i.e., V _in-supply-voltage and ground-level), is presented. In a much broader sense, digital circuits can be used for time-domain processing instead of conventional analog signal processing. In this study, an all-digital 6- to 16-bit adaptive sensor-interface ADC is experimentally evaluated for high-resolution and low-power operation along with high scalability. The circuit architecture is completely digital, using a ring-delay-line (RDL) driven by an input voltage V _in as its power supply. Resolutions can be controlled by setting its conversion time T _cv, resulting in 16 bit (1 kS/s, 34 μW) and 6 bit (1 MS/s, 48 μW) with a prototype IC in a low-cost 0.65-μm (650-nm) digital CMOS, achieving the sensor digitizer (sensor-digitization product) of a pressure sensor ASIC. The all-digital structure has been scaled into a 0.18-μm technology, and the test IC presented a higher performance with 28 μV/LSB (160-kS/s). Finally, as an RF digitization application, the circuit is demonstrated to realize the time-domain processing of an RF signal, working as both mixer and ADC, achieving minimum/maximum detectable sensitivity of 0.7-μVrms/100-mVrms, respectively, for a 40-kHz sine wave at the LNA input terminal of a 0.18-μm digital CMOS one-chip radio-controlled clock receiver IC.     

A semi-digital delay-locked loop using an analog-based finite state machine

This brief describes a low-power full-rate semi-digital delay-locked loop (DLL) architecture using an analog-based finite state machine (AFSM) and a polyphase filter. The AFSM architecture uses low-power analog blocks to map high-frequency loop feedback information to low frequency, thus reducing the total power required for digital signal processing and for the macro as a whole. The polyphase filter generates full-rate multiphase outputs for a phase rotator, hence a reference clock of the semi-digital DLL can be generated by any reference source including a phase-locked loop with an LC voltage-controlled oscillator. The prototype semi-digital DLL in 0.12-/spl mu/m CMOS exhibits less than 10/sup -12/ bit error rate at 3.2 Gb/s consuming 60 mW.     

Low-Power,Low-Complexity Bit-Serial VLSI Architecture for 1D Discrete Wavelet Transform

The discrete wavelet transform (DWT) is an upcoming compression technique that has been selected for MPEG-4 and JEPG 2000, because it has no blocking effects and it efficiently determines the frequency property of the temporary signals. In this paper, we propose a low-complexity, low-power bit-serial DWT architecture, employing a two-channel lattice-based quadrature mirror filter (QMF). The filter consists of four lattices (filter length = 8), and we determine the quantization bit for the coefficients using a fixed-length peak signal-to-noise ratio analysis and propose the architecture of the bit-serial multiplier with a fixed coefficient. The canonical signed digit encoding for the coefficients is applied to minimize the number of nonzero bits, thus reducing the hardware complexity. The proposed folded one-dimensional DWT architecture processes the other resolution levels during idle periods by decimations, and it provides efficient scheduling. The proposed architecture requires only flip-flops and full adders. This architecture has been designed and verified by the Verilog HDL and synthesized using the Synopsys Design Compiler with the DongbuAnam 0.18 μm Standard Cell Library. The maximum throughput is 393 Mbps at 450 MHz with a latency of 16 clocks, and the gate count is about 5K in equivalent two-input NAND gates. The dynamic power is 7.02 mW at 1.8 V. The data scheduling using a data dependency graph, and the performance, power, and required hardware cost are discussed.     

A 2.1 μW 80 dB SNR DT ΔΣ modulator for medical implant devices in 65 nm CMOS

This paper presents a simple and robust low-power ΔΣ modulator for accurate ADCs in implantable cardiac rhythm management devices such as pacemakers. Taking advantage of the very low signal bandwidth of 500 Hz which enables high oversampling ratio, the objective is to obtain high SNDR and low power consumption, while limiting the complexity of the modulator to a second-order architecture. Significant power reduction is achieved by utilizing a two-stage load-compensated OTA as well as the low-V_T devices in analog circuits and switches, allowing the modulator to operate at 0.9 V supply. Fabricated in a 65 nm CMOS technology, the modulator achieves 80 dB peak SNR and 76 dB peak SNDR over a 500 Hz signal bandwidth. With a power consumption of 2.1 μW, the modulator obtains 0.4 pJ/step FOM. To the authors’ knowledge, this is the lowest reported FOM, compared to the previously reported second-order modulators for such low-speed applications. The achieved FOM is also comparable to the best reported results from the higher-order ΔΣ modulators.     

An ultra-low-voltage ultra-low-power CMOS active mixer

The scaling of CMOS technology has greatly influenced the design of analog and radio-frequency circuits. In particular, as technology advances, due to the use of lower supply voltage the available voltage headroom is decreased. In this paper, after a brief overview of conventional low-power CMOS active mixer structures, we introduce an active mixer structure with sub-mW-level power consumption that is capable of operating from a supply voltage comparable or lower than the threshold voltage of the transistor. In addition, the proposed architecture provides a performance and conversion gain (CG) that compares favorably or exceeds those of the state-of-the-art designs. As a proof-of-concept, a wide-band DC to 8.5 GHz down-conversion mixer is designed and fabricated in a 90-nm CMOS process. Measurement results show that the mixer achieves a CG as high as 18 dB while consuming 98 μW from a 0.3-V supply.     

Two's complement computation sharing multiplier and its applications to high performance DFE

We present a novel computation sharing multiplier architecture for two's complement numbers that leads to high performance digital signal processing systems with low power consumption. The computation sharing multiplier targets the reduction of power consumption by removing redundant computations within system by computation reuse. Use of computation sharing multiplier leads to high-performance finite impulse response (FIR) filtering operation by reusing optimal precomputations. The proposed computation sharing multiplier can be applicable to adaptive and nonadaptive FIR filter implementation. A decision feedback equalizer (DFE) was implemented based on the computation sharing multiplier in a 0.25-/spl mu/ technology as an example of an adaptive filter. The performance and power consumption of the DFE using a computation sharing multiplier is compared with that of DFEs using a Wallace-tree and a Booth-encoded multiplier. The DFE implemented with the computation sharing multiplier shows improvement in performance over the DFE using a Wallace-tree multiplier, reducing the power consumption significantly.     

Automatic ocular artifact removal from EEG data using a hybrid CAE-RLS approach

Traditional methods for removing ocular artifacts (OAs) from electroencephalography (EEG) signals often involve a large number of EEG electrodes or require electrooculogram (EOG) as the reference, these constraints make subjects uncomfortable during the acquisition process and increase the complexity of brain-computer interfaces (BCI). To address these limitations, a method combining a convolutional autoencoder (CAE) and a recursive least squares (RLS) adaptive filter is proposed. The proposed method consists of offline and online stages. In the offline stage, the peak and local mean of the four-channel EOG signals are automatically extracted to obtain the CAE model. Once the model is trained, the EOG channels are no longer needed. In the online stage, by using the CAE model to identify the OAs from a single-channel raw EEG signal, the identified OAs and the given raw EEG signal are used as the reference and input for an RLS adaptive filter. Experiments show that the root mean square error (RMSE) of the CAE-RLS algorithm and independent component analysis (ICA) are 1.253 3 and 1.254 6 respectively, and the power spectral density (PSD) curve for the CAE-RLS is similar to the original EEG signal. These experimental results indicate that by using only a couple of EEG channels, the proposed method can effectively remove OAs without parallel EOG records and accurately reconstruct the EEG signal. In addition, the processing time of the CAE-RLS is shorter than that of ICA, so the CAE-RLS algorithm is very suitable for BCI system.     

A Low-Power Digit-Based Reconfigurable FIR Filter

In this brief, we present a digit-reconfigurable finite-impulse response (FIR) filter architecture with a very fine granularity. It provides a flexible yet compact and low-power solution to FIR filters with a wide range of precision and tap length. Based on the proposed architecture, an 8-digit reconfigurable FIR filter chip is implemented in a single-poly quadruple-metal 0.35-$muhbox m$CMOS technology. Measurement results show that the fabricated chip operates up to 86 MHz when the filter draws 16.5 mW of power from a 2.5-V power supply.     

A flexible adaptive FIR filter VLSI IC

The architecture and features of the Motorola DSP56200 are described. The DSP56200 is an algorithm-specific cascadable digital signal processing peripheral designed to perform the computationally intensive tasks associated with finite impulse response (FIR) and adaptive FIR digital filtering applications. The DSP56200 is implemented in high-performance, low-power 1.5-μm HCMOS technology and is available in a 28-pin DIP package. The on-chip computation unit includes a 97.5-ns 24-bit×24-bit coefficient RAM, and a 256-bit×16-bit data RAM. Three modes of operation allow the part to be used as a single, dual, or single adaptive FIR filter, with up to 256 taps per chip. In the adaptive mode, the part performs the FIR filtering and least-mean-square (LMS) coefficient update operations for a single tap in 195 ns, permitting use of the part as a 19-kHz sampling rate, 256-tap adaptive FIR filter. A programmable DC tap, coefficient leakage, and adaptation coefficient parameters in the adaptive FIR mode allow the DSP56200 to be used in a wide variety of adaptive FIR filtering applications. The performance of the part in an echo canceler configuration is presented. Typical applications of the part are also described