斜阶跃信号激励下的RLC互连线时延模型

文章对斜阶跃信号激励下的RLC互连线时延模型进行了研究.用改进1阶模型逼近传输线的传输函数,得到了比较简洁的时延解析式.该模型计算所得的结果与SPICE仿真结果的误差小于5%.     

Exponentially tapered H-tree clock distribution networks

Exponentially tapered interconnect can reduce the dynamic power dissipation of clock distribution networks. A criterion for sizing H-tree clock networks is proposed. The technique reduces the power dissipated for an example clock network by up to 15% while preserving the signal transition times and propagation delays. Furthermore, the inductive behavior of the interconnects is reduced, decreasing the inductive noise. Exponentially tapered interconnects decrease by approximately 35% the difference between the overshoots in the signal at the input of a tree. As compared to a uniform tree with the same area overhead, overshoots in the signal waveform at the source of the tree are reduced by 40%.     

Analytical models and algorithms for the efficient signal integrity verification of inductance-effect-prominent multicoupled VLSI circuit interconnects

Novel signal integrity verification models and algorithms for inductance-effect- prominent RLC interconnect lines are developed by using a traveling-wave-based waveform approximation (TWA) technique. The multicoupled line responses are decoupled into the eigenmodes of the system in order to exploit the TWA technique. Then, the response signals are mathematically represented by the linear combination of each eigenmode response based on TWA, followed by reporting the signal integrity models and algorithms for the multicoupled lines. The signal integrity of VLSI circuit interconnects is complicatedly correlated with input signal switching-patterns, layout geometry, and termination conditions. It is shown that the technique can be efficiently employed for complicated multicoupled interconnect lines with various termination conditions and the signal transients based on the technique have excellent agreement with SPICE simulations. Thus, with the proposed technique, the switching-dependent signal delay, crosstalk, ringing, and glitches of the inductance-effect-prominent RLC interconnect lines can be accurately as well as efficiently determined.     

基于参数化模型的FPGA时钟网络设计和优化

本文在FPGA时钟网络（Clock Distributed Network,CDN）关键结构尺寸的参数化建模基础上,提出一种针对全定制FPGA CDN的设计和优化方法.本文所建立的参数化模型将结构尺寸分为拓扑结构和电路与互连两类,分别给出了这两类尺寸参数的设计原则.在标准CMOS 0.13μm工艺下,对H树型、鱼骨型以及混合型三种类型时钟网络设计了2组结构参数,分别代表优化前和优化后,对比分析延时、偏斜、功耗和面积等性能参数.实验结果显示：混合型结构在绝对延时和时钟偏斜上减小最多,分别达到20.89%和63.20%;鱼骨型结构的面积减小达到50.14%;H树型结构的绝对延时和功耗则均降低了7.37%和8.33%.以上结果充分证明了本文所提设计优化方法的有效性.     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

An innovative interconnect structure with improved Elmore delay estimation model for deep submicron technology

With advancements in technology, size and speed have been the important facet in VLSI interconnects. The channel length of the device reduces to tens of nanometers, as the technology is transferring to the deep submicron level. This leads to the requirement of long interconnects in VLSI chips. Interconnects are known as the basic building block that can vary from size to size. They provide a connection between two or more blocks and have scaling problems that an IC designer faces while designing. As scaling increases, the impact of interconnect in the VLSI circuits became even more important. It controls all the important electrical characteristics on the chip. With scale-down technology, interconnects not only become closer with each other but their dimensions also change which can directly impact the circuit parameters. Certain RC models have already been defined to control these parameters but in this paper, authors have proposed a new improved Elmore delay estimation model (RC) to reduce delay and power consumption in interconnect circuits. An optimized Elmore delay calculation was performed for uniform and non-uniform wires to reduce the time constant of the interconnect circuits. Further, the proposed model is estimated and verified theoretically. A new improved RC model is compared to the designed π-model that shows remarkable results. We also observed the linear relationship of power consumption and delay for both the RC models and found that in π-model, upon decreasing the length of wire the power first increases then decreases but in the proposed model, the power first increases then remain constant and then further increases upon increasing the length of wire. Our proposed model shows the remarkable values as the average percentage improvement of power is 75.167% and delay as 74.714% is achieved using a uniform distribution.

     

A multilevel parasitic interconnect capacitance modeling andextraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays     

An improved RC model for VLSI interconnects with applications to buffer insertion

A general platform to generate the RC, RLC and RLCG models of interconnects using global approximation method, two-port networks, and asymptotic waveform evaluation (AWE) is presented. Using the delay of transmission-line-modeled interconnects from HSPICE as a bench mark, we show that among all 18 models studied, the π-configuration of AWE-RLC model yields the best accuracy. To reduce complexity subsequently computational cost without sacrificing accuracy, the AWE-RLC model is mapped to a complex RC model using moment matching. The complex RC model is further mapped to an improved RC model utilizing the principle of charge reservation. The improved RC model is employed to estimate the delay of long interconnects with buffer insertion. As compared with the conventional RC model, the improved RC model reduces the delay of interconnects with buffer insertion, the number of buffers, and the size of the buffer by 20.5, 24, and 32 %, respectively.     

Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs

This article analyses the effect of coupling parasitics and CMOS gate driver width on transition time delay of coupled interconnects driven by dynamically switching inputs. Propagation delay through an interconnect is dependent not only on the technology/topology but also on many other factors such as input transition time, load characteristic, driving gate dimensions and so on. The delay is affected by rise/fall time of the signal, which in turn is dependent on the driving gate and the load presented to it. The signal transition time is also a strong function of wire parasitics. This article addresses the different issues of signal transition time. The impact of inter-wire parasitics and driver width on signal transition time are presented in this article. Furthermore, the effect of unequal transition time of the inputs to interconnect lines on crosstalk noise and delay is analysed. To demonstrate these effects, two distributed RLC lines coupled capacitively and inductively are taken into consideration. The simulations are run at three different technology nodes, viz. 65 nm, 90 nm and 130 nm.     

Monolayer metallic nanotube interconnects: promising candidates for short local interconnects

Mono- or bi-layer metallic single-wall carbon nanotube interconnects have lateral capacitances more than four times smaller than those of copper interconnects. The resistance and time-of-flight of these monolayer nanotubes would be larger than that of copper interconnects. For short lengths, however, driver resistance is quite dominant, and latency is determined by interconnect capacitance. Monolayer nanotube interconnects are therefore promising candidates for local interconnects. The average capacitance per unit length of these nanotube interconnects can be 50% smaller than that of copper interconnects and that leads to significant saving in power dissipation.     

Current-mode signaling in deep submicrometer global interconnects

This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines, simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a wide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs with arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage and current mode repeater insertion for long global deep submicrometer interconnects is presented.     

Delay analysis of buffer inserted sub-threshold interconnects

In this paper, an analysis of interconnect delay minimization by CMOS buffer insertion in sub-threshold regime is presented. Analytical expressions are developed to calculate the total delay and optimum number of buffers required for delay minimization in sub-threshold interconnects. Considering delay minimization by buffer insertion, the effects of voltage-scaling on the delay and optimum number of buffers have been analyzed. It is demonstrated that voltage scaling in sub-threshold regime reduces the number of buffers required to attain the minimum delay. This is one more advantage of voltage-scaling in addition to the usual reduction in power dissipation, in the sense that lesser silicon area is consumed. For a wide variety of typical interconnect loads, analytically obtained results are in good agreement with SPICE extracted results for most of the cases more than 90 %. Finally, the variability analysis of sub-threshold interconnects is investigated using Monte Carlo analysis.     

Timing-driven via placement heuristics for three-dimensional ICs

The dependence of the interconnect delay on the interplane via location in three-dimensional (3-D) ICs is investigated in this paper. The delay of these interconnects can be significantly decreased by optimally placing the interplane vias. The via locations that minimize the propagation delay of two-terminal interconnects consisting of multiple interplane vias under the distributed Elmore delay model are determined. For interconnect trees, the interplane via locations that minimize the summation of the weighted delay of the sinks of the tree are also determined. For these interconnect structures, the interplane via locations are obtained both through geometric programming and near-optimal heuristics. Placement constraints are imposed such that the path is negligibly affected. The proposed heuristics are used to implement efficient algorithms that exhibit lower computational times as compared to general optimization solvers with negligible loss of optimality. Various interplane via placement scenarios are considered. Simulation results indicate delay improvements for relatively short point-to-point interconnects of up to 32% with optimally placed interplane vias. For interconnect trees, the maximum improvement in delay for optimally placed interplane vias is 19%. The proposed algorithms can be integrated into a design flow for 3-D circuits to enhance placement and routing where timing is a primary design criterion.     

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.     

一种65nm CMOS互连线串扰分布式RLC解析模型

基于65nm CMOS工艺,综合考虑电容耦合与电感耦合效应,提出了一种互连线耦合串扰分布式RLC解析模型.采用函数逼近理论与降阶技术,在斜阶跃输入信号下,提出了被干扰线远端的串扰数值表达式.基于65nm CMOS工艺,对不同的互连耦合尺寸下的分布式RLC串扰解析模型和Hspice仿真结果进行了比较,误差绝对值都在2.50%内,能应用于纳米级SOC的计算机辅助设计.     

Inductance model and analysis methodology for high-speed on-chip interconnect

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures.     

基于单壁碳纳米管束的三维互连线设计与分析

Metallic carbon nanotubes(CNTs) have been proposed as a promising alternative to Cu interconnects in future integrated circuits(ICs) for their remarkable conductive, mechanical and thermal properties. Compact equivalent circuit models for single-walled carbon nanotube(SWCNT) bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional(3D) ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respectively.     

Enhanced Low Complex Double Error Correction Coding with Crosstalk Avoidance for Reliable On-Chip Interconnection Link

As the technology scales down, shrinking geometry and layout dimension, on- chip interconnects are exposed to different noise sources such as crosstalk coupling, supply voltage fluctuation and temperature variation that cause random and burst errors. These errors affect the reliability of the on-chip interconnects. Hence, error correction codes integrated with noise reduction techniques are incorporated to make the on-chip interconnects robust against errors. The proposed error correction code uses triplication error correction scheme as crosstalk avoidance code (CAC) and a parity bit is added to it to enhance the error correction capability. The proposed error correction code corrects all the error patterns of one bit error, two bit errors. The proposed code also corrects 7 out of 10 possible three bit error patterns and detects burst errors of three. Hybrid Automatic Repeat Request (HARQ) system is employed when burst errors of three occurs. The performance of the proposed codec is evaluated for residual flit error rate, codec area, power, delay, average flit latency and link energy consumption. The proposed codec achieves four magnitude order of low residual flit error rate and link energy minimization of over 53 % compared to other existing error correction schemes. Besides the low residual flit error rate, and link energy minimization, the proposed codec also achieves up to 4.2 % less area and up to 6 % less codec power consumption compared to other error correction codes. The less codec area, codec power consumption, low link energy and low residual flit error rate make the proposed code appropriate for on chip interconnection link.     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.     

分析多芯片组件互连延时的一种新方法

随着多芯片组件工作频率的不断增加，信号延时受互连的影响越来越大，互连已成为决定系统性能的主要因素。延时与冲激响应有着密切的联系，本文采用系统冲激响应的低阶矩，基于双极点近似对互连的延时特性进行了研究。与已有的方法比较，本文的方法提高了极点选择的稳定性，适用于复杂的互连网络。举例证明了这种方法的有效性。