Low Voltage Low Cost Quadrature Oscillator Based on Active Inductor

This paper presents a new low voltage low cost quadrature oscillator, which consists of two LC negative oscillators based on active inductor. In this quadrature oscillator, the back-gates of the core transistors are used as coupling terminals to provide the quadrature outputs. The proposed floating active inductor has a two layer transistor structure. The quadrature oscillator has been implemented with the chart 0.18  \(\upmu \) m CMOS technology. At the supply voltage of 1.2 V, the total power consumption is 16 mW. The phase noise at 1 MHz frequency offset is \(-\) 111.8 dBc/Hz at the oscillation frequency of 3.946 Hz.     

A 2.4 GHz high-performance CMOS differential quadrature relaxation oscillator

In this paper, the effects that limit the performance of practical implementations of RC relaxation oscillators are investigated. The insights gained are used to suggest a topology for high-frequency quadrature relaxation oscillators with closer-to-optimal performance. The proposed oscillator uses a modified latch to improve the switching speed without increasing the power consumption. Moreover, the new topology avoids static current sources, maximizes the voltage swing and has an active coupling structure without static power consumption that reduces the circuit phase-noise. Experimental results show that the oscillator operates in relaxation mode at 2.4 GHz and achieves a FoM of \(\mathrm {-162\,dBc/Hz}\), which is, as far as the authors know, the best FoM for relaxation oscillators operating in the GHz range.     

A Giga-Hertz-Range MOS Current-Tunable Sinusoidal Oscillator with Inherent Automatic Amplitude Control

A new all MOS current-mode current-tunable sinusoidal oscillator is proposed. Using a standard 0.8 CMOS fabrication process, an oscillation frequency of greater than 1 GHz can be achieved, with only 3.3 V supply voltage, and with less than 5–mW power consumption. Most importantly, a symmetrical automatic amplitude control or AGC function is also inherent in the circuit.     

A Low-Voltage and Low-Power 3-GHz CMOS LC VCO for S-Band Wireless Applications

A fully integrated 0.18- \(\upmu \hbox {m}\) CMOS LC-tank voltage-controlled oscillator (VCO) suitable for low-voltage and low-power S-band wireless applications is proposed in this paper. In order to meet the requirement of low voltage applications, a differential configuration with two cross-coupled pairs by adopting admittance-transforming technique is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed VCO can operate at 0.4 V supply voltage. Despite the low power supply near threshold voltage, the VCO achieves wide tuning range by using a voltage-boosting circuit and the standard mode PMOS varactors in the proposed oscillator architecture. The simulation results show that the proposed VCO achieves phase noise of \(-\) 120.1 dBc/Hz at 1 MHz offset and 39.3 % tuning range while consuming only \(594~\upmu \hbox {W}\) in 0.4 V supply. Figure-of-merit with tuning range of the proposed VCO is \(-\) 192.1 dB at 3 GHz.     

Low-voltage nanopower clock generator for RFID applications

The design of an on-chip RC-based oscillator, implemented in a standard BiCMOS process, without any external component, is presented. The proposed oscillator provides a clock signal at a frequency of 50 kHz with a temperature coefficient smaller than 0.3%/^°C over a temperature range from 0 to , without any external trimming. The proposed oscillator operates with a supply voltage of 0.8 V and has a power consumption of at room temperature. The chip area is .     

A SiGe:C BiCMOS dual down converter for MIMO wireless infrastructure with configurable current consumption and linearity

This paper presents a dual RF down converter suitable for Multiple-Input and Multiple-Output infrastructure applications. The proposed architecture features a CMOS tapered buffer as local oscillator driver with a programmable supply voltage, provided by an embedded low dropout regulator. This approach allows scaling current consumption depending on linearity requirements. The RF path uses a balun with programmable tuning capacitors for single-to-differential signal conversion and \(50\text{-}\Omega\) input matching. A MOSFET passive mixer and a high-voltage (5 V) bipolar intermediate frequency amplifier complete the signal path. The circuit is fabricated in a SiGe:C BiCMOS process, occupies an area of \(2.8\, \text{mm} \, \times \, 2.5\, \text{mm}\), and has been assembled in a \(6\, \text{mm} \, \times \,6\, \text{mm}\), 40-pin, quad flat no-lead (QFN) package.     

A Low Voltage and Low Power Bottom-Series Coupled Quadrature VCO

This letter presents a new low power quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) with split-source tail inductors. The bottom-series coupling transistors are in parallel with the tail inductors and require no dc voltage headroom. The proposed CMOS QVCO has been implemented with the TSMC 0.18 $mu{rm m}$ CMOS technology and the die area is $0.512times 1.065 {rm mm}^{2}$. At the supply voltage of 1.1 V, the total power consumption is 2.545 mW. The free-running frequency of the QVCO is tunable from 4.38 to 4.71 GHz as the tuning voltage is varied from 0.0 V to 0.6 V. The measured phase noise at 1 MHz frequency offset is $-$120.8 dBc/Hz at the oscillation frequency of 4.4 GHz and the figure of merit (FOM) of the proposed QVCO is $-$ 189.61 dBc/Hz.      

Multi-Modulus LC Injection-Locked Frequency Dividers Using Single-Ended Injection

A new wide-locking range multi-modulus LC-tank injection locked frequency divider (ILFD) is proposed and was fabricated in a 0.18 $mu {rm m}$ CMOS process. The ILFD circuit is realized with a complementary MOS LC-tank oscillator and an injection composite composed of an inductor in series with an injection MOS. The two output terminals of the injection composite are connected to the resonator outputs. The ILFD can be used as a first-harmonic oscillator (ILO), even-modulo or odd-modulo oscillator depending upon the incident frequency of injection signal. At the supply voltage of 1.5 V, the free-running frequency is from 4.85 to 5.13 GHz, the current and power consumption of the divider without buffers are 2.78 and 4.17 mW, respectively. At the incident power of 0 dBm, the locking range in the divide-by-1(2, 3, 4) mode is from the incident frequency 3.72 to 8.69 (8.42 to 10.95, 13.66 to 16.03, 19.13 to 20.5) GHz.      

A 0.22 V Quadrature VCO in 90 nm CMOS Process

This letter presents an ultra-low voltage quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two low-voltage voltage-controlled oscillators (VCOs) with the body dc biased at the drain bias through a resistor. The superharmonic and back-gate coupling techniques are used to couple two differential VCOs to run in quadrature. The proposed CMOS QVCO has been implemented with the UMC 90 nm CMOS technology and the die area is 0.827 $, times ,$0.913 mm $^{2}$. At the supply voltage of 0.22 V, the total power consumption is 0.33 mW. The free-running frequency of the QVCO is tunable from 3.42 to 3.60 GHz as the tuning voltage is varied from 0.0 to 0.3 V. The measured phase noise at 1 MHz offset is ${-}112.97$ dBc/Hz at the oscillation frequency of 3.55 GHz and the figure of merit (FOM) of the proposed QVCO is about ${-}188.79$ dBc/Hz.      

Analysis and Design of a Wide-Tuning-Range VCO With Quadrature Outputs

A quadrature voltage-controlled oscillator (QVCO) with a wide tuning range is proposed and implemented in the TSMC 0.18- $mu{rm m}$ CMOS process. The said QVCO uses a cross-coupled structure and a current-reuse technology to produce the quadrature signal and to save power consumption and area, respectively. Based on our measurement, the phase noise with 1-MHz offset from the carrier frequency of 3.6 GHz is $-$ 114 dBc/Hz and the proposed QVCO has a wide-band tuning range of 3.6–4.9 GHz. Also, the maximal phase error and power imbalance are less than 5$^{circ}$ and 1.5 dB, respectively, and the power consumption is 8 mW at 2-V power supply voltage.      

Low Voltage Rail to Rail CMOS Current Feedback Operational Amplifier and its Applications for Analog VLSI

This paper presents a new CMOS current feedback operational amplifier (CFOA) with rail to rail swing capability at all terminals. The circuit operates as a class AB for lower power consumption. Besides operating at low supply voltages of ±1.5 V, the proposed CFOA has a standby current of 200 A. The proposed CFOA circuit is thus a versatile building block for low voltage low power applications. The applications of the CFOA to realize a transconductor/multiplier cell, MOS-C differential integrator, MOS-C bandpass filter and MOS-C oscillator are given. PSpice simulations based on 1.2 m level three parameters obtained from MOSIS are given.     

Low-power integrating frequency difference-to-voltage converter with applications in injection-locked FLL

This paper presents a new integrating frequency difference-to-voltage converter (iFDVC) with applications in injection-locked frequency-locked loops (FLLs). The proposed iFDVC features low power consumption, high frequency sensitivity, a zero static frequency error, and a low sensitivity to PVT (process, voltage, and temperature) uncertainty. A detailed analysis of the time and frequency-domain behaviour of the iFDVC is presented. The effectiveness of the iFDVC is studied by embedding it in a FLL with a relaxation oscillator. To shorten locking process without sacrificing frequency accuracy, injection-locking is employed. The loop dynamics of the FLL with and without injection-locking are analyzed. The simulation results of an injection-locked FLL with the proposed iFDVC designed in an IBM 130 nm 1.2 V CMOS technology demonstrate that the injection-locked FLL has a lock time 4.5 times smaller and an acquisition range 59 times larger as compared with those of the corresponding FLL without injection-locking while consuming 60 \(\upmu\)W only. The iFDVC was also implemented using off-shelf components and its performance was validated using measurement results.     

A Wide Tuning Range 69 GHz Push-Push VCO Using 0.18 CMOS Technology

A wide tuning range V-band push-push CMOS voltage controlled oscillator (VCO) is proposed in this study. A new core complementary Colpitts structure was adopted in a 0.18 $mu{rm m}$ CMOS process to reduce dc power consumption and to improve tuning range owing to the reduction weighting of FET induced capacitance of L-C tank. The designed VCO oscillates from 64.2 to 69.4 GHz with a 5.2 GHz tuning range under a control voltage range of 1.2 V. The measured phase noise at 1 MHz offset is $-76.23~ {rm dBc}/{rm Hz}$ at 69.39 GHz. The power consumption of the VCO core is only 27.52 mW.      

Design and implementation of all MOS micro-power voltage reference circuit

In this work we are proposing the all MOST based reference voltage generating circuit, which utilizes the classical principle of addition of two voltages with opposite temperature coefficients. The targeted application of the proposed circuit is a low-dropout regulator which is used in a RF energy harvesting system. The proposed voltage reference circuit is implemented using a standard 0.18 μm CMOS technology. It generates the average reference voltage of 543.658 mV with an average temperature coefficient of 17.43 ppm/°C in the temperature range of ?40 to +85 °C, for the operating supply voltage ranging from 1.25 to 2 V. The maximum power consumption of the proposed architecture is ≈1.5 μW, including power dissipation in bias circuitry and the reference voltage generating core at 2 V supply voltage. The averaged measured line regulation is 1.642 mV/V. The measured power-supply rejection ratio without any filtering capacitor at 100 Hz and 1 MHz are ?62.24 and ?18.94 dB, respectively. Additionally, the measured noise density without any filtering capacitor at 10 Hz and 100 KHz is 20.54 and \(0.30\,\upmu \hbox {V}/\sqrt{\hbox{Hz}}\) , respectively. The proposed circuit has silicon area of ≈0.007 mm².     

A highly linear and fully-integrated FMCW synthesizer for 60 GHz radar applications with 7 GHz bandwidth

A highly linear and fully-integrated frequency-modulated continuous-wave (FMCW) generator based on a fractional-N phase-locked loop (PLL) that is able to synthesize modulation schemes in 57–64 GHz range is proposed in this paper. The fractional-N PLL employs Colpitts voltage-controlled oscillator (VCO) at 60 GHz with 13.5% tuning range. Automatic amplitude and frequency calibrations are implemented to avoid drifts due to process, voltage and temperature variations and to set the center frequency of the VCO. Five-stage multi-modulus divider is used for division ratio switching, controlled by the sigma-delta (\(\Sigma \Delta\)) modulator MASH 1-1-1. The frequency sweep (chirp) bandwidth and duration are fully programmable via serial peripheral interface allowing up to 16 different chirps in complex modulation scheme. The PLL reference signal is 250 MHz provided by external low-noise signal generator which is also used for digital modules clock. The overall PLL phase noise is lower than ?80 dBc/Hz at 10 kHz offset and the chirp linearity is better than 0.01%. The complete FMCW synthesizer is implemented and verified as a stand-alone chip in a commercially available SiGe HBT 130 nm BiCMOS technology. The total chip area is \(2.04\,\text {mm}^2\), and the total power consumption is 280 mW.     

Analysis and Implementation of a 0.9-V Voltage-Controlled Oscillator With Low Phase Noise and Low Power Dissipation

A voltage-controlled oscillator (VCO) with low phase noise and low power dissipation for IEEE 802.11b is proposed. A negative resistance multiple-gated circuit with a bypass capacitor is adopted to improve phase noise. The chip is implemented in 0.18-$mu{hbox {m}}$ CMOS process under a supply voltage of 0.9 V and power consumption of 2.7 mW. Its measured results show that the VCO has a phase noise of $-$122.3 dBc/Hz at 1-MHz offset frequency from the carrier frequency, and the tuning frequency from 2.17 to 2.73 GHz can be obtained under the tuning voltage of $-$0.9 to 0.9 V. The theoretical analysis and design consideration are also conducted in detail to show the benefits of the proposed VCO.      

An Amplitude-Balanced Current-Reused CMOS VCO Using Spontaneous Transconductance Match Technique

A 3.5 GHz, 0.18 $mu{rm m}$ CMOS current-reused voltage-controlled oscillator (VCO) with very high amplitude balance is presented. While the current-reused VCO can dramatically save dc power consumption, it has the drawback of output amplitude imbalance resulting from the asymmetric circuit structure. A spontaneous transconductance match (STM) technique is proposed to balance the transconductance of nMOS and pMOS transistors by the imbalance-induced voltage at the center-tapped point of the tank inductor. This transconductance match takes place spontaneously with the occurrence of signal imbalance such that imbalances can be instantly eliminated. The measured amplitude imbalance ratio is less than 0.7% over the entire tuning range of 2.93 to 3.62 GHz, significantly reduced from 3% of the VCO without STM. The power consumption is as low as 1.65 mW from a 1.5 V supply. The phase noise is $-$ 122 dBc/Hz at 1 MHz offset. A very high FOM of $-$195.7 dBc/Hz is achieved.      

High-Accuracy Time-Mode Duty-Cycle-Modulation-Based Temperature Sensor for Energy-Efficient System Applications

This paper presents a new time-mode duty-cycle-modulation-based high-accuracy temperature sensor. Different from the well-known \({\varSigma }{\varDelta }\) ADC-based readout structure, this temperature sensor utilizes a temperature-dependent oscillator to convert the temperature information into temperature-related time-mode parameter values. The useful output information of the oscillator is the duty cycle, not the absolute frequency. In this way, this time-mode duty-cycle-modulation-based temperature sensor has superior performance over the conventional inverter-chain-based time domain types. With a linear formula, the duty-cycle output streams can be converted into temperature values. The design is verified in 65nm standard digital CMOS process. The verification results show that the worst temperature inaccuracy is kept within 1\(\,^{\circ }\mathrm{C}\) with a one-point calibration from \(-\)55 to 125 \(^{\circ }\mathrm{C}\). At room temperature, the average current consumption is only 0.8 \(\upmu \)A (1.1\(\,\upmu \)A in one phase and 0.5 \(\upmu \)A in the other) with 1.2 V supply voltage, and the total energy consumption for a complete measurement is only 0.384 \({\hbox {nJ}}\).     

RF Oscillator Based on a Passive RC Bandpass Filter

A passive RC bandpass filter (BPF) based voltage-controlled-oscillator (VCO) operating at 2.5 GHz is presented. In GHz frequency range, a preferred type of an oscillator is either an LC oscillator or a ring oscillator. An LC oscillator exhibits an excellent phase noise performance while its fabrication cost is expensive due to the inductors. On the other hand, a ring oscillator can be built with standard CMOS devices resulting in a cheap fabrication cost. However, it has a poor phase noise and jitter performance and is sensitive to power supply noise. This paper proposes a RC BPF-based oscillator. Its property is closer to a LC oscillator rather than a ring oscillator and, as a result, improves the jitter performance due to power supply noise. Also, it can be fabricated in a standard CMOS process since there is no inductor. To prove the proposed concept, a RC BPF-based oscillator was designed and fabricated in a standard 0.13-$mu{hbox {m}}$ CMOS technology. An operating frequency of 2.5 GHz and phase noise of $-$ 95.4 dBc/Hz at 1$~$MHz offset was measured. Power consumption was 2.86 mW from a 1.3$~$ V supply voltage.      

Low phase-noise VCO utilizing modified symmetric load and partial positive feedback for FDSM

The voltage-controlled oscillator (VCO) in frequency-based $\Updelta\Upsigma$ modulator (FDSM) systems behaves as a voltage-to-phase integrator converting an analog input voltage to phase information. Tuning range and phase noise are the most important factors of the basic design of a VCO in FDSM systems. In this paper a novel low phase-noise and wide tuning-range differential VCO based on a differential ring oscillator with modified symmetric load and a partial positive feedback in the differential delay cell is presented. The VCO is combined with a new bias circuit and implemented using 90 nm CMOS process technology. By using modified NMOS symmetric loads and a PMOS tail for delay cells, the VCO phase noise can be reduced with more than 13 dB compared to that of the conventional approach, achieving ?125 dBc/Hz at 500 kHz offset from the center frequency of 450 MHz. The wide tuning-range by using two added transistors (parallel with the active loads) increases the operating frequency range by about 22%, while the partial positive feedback provides the necessary bias condition for the circuit to oscillate. The designed VCO operating at a low power supply voltage of 0.6V can achieve low power consumption of 670???W at oscillation frequency of 800 MHz and good linearity reducing harmonic distortion in the $\Updelta\Upsigma$ modulator.