阈值电压对超深亚微米SRAM存储单元SNM的影响

采用基于物理模型的 α指数 MOSFET模型 ,对超深亚微米 (VDSM:Very Deep Submicron) SRAM存储单元的静态噪声容限 (SNM:Static Noise Margin)进行了解析分析 ,分析中考虑了随机工艺涨落造成的VDSM SRAM存储单元阈值失配对 SNM的影响 ,结果与 HSPICE仿真相符 ;文中同时分析了栅宽与 SNM的关系 ,其结论与实验结果一致 ,并给出了 VDSM SRAM存储单元设计中应注意的问题     

45nm工艺下8管双阈值SRAM单元的研究

比较分析了8管SRAM单元在不同双阈值组合情形下的性能,为不同需求的设计者提供了在静态噪声容限(SNM)、漏功耗和延迟之间做出合理权衡的参考。仿真结果表明,组合C8具有最大的SNM,高阈值晶体管Mnl可以有效抑制漏电流。最后,分析了不同组合下的读写延迟时间,并给出了延迟差异的原因。     

基于九管存储单元的嵌入式SRAM设计

为了解决深亚微米及纳米尺寸下SRAM设计在可靠性及其他性能方面所面临的挑战,在分析不同存储单元的基础上,提出了一种优化的具有高稳定性的九管存储单元,并采用9管存储阵列,设计了一款高可靠性的512×32位SRAM.基于TSMC 0.18 μm CMOS工艺,对电路进行仿真.实验结果表明:该SRAM在250 MHz工作频率下,存储阵列中数据的读写稳定性高,阵列功耗为7.76 mW,数据读出时间为0.86 ns,电路面积仅比采用传统6管单元增加13.5%.     

一种基于位交错结构的亚阈值10管SRAM单元

提出了一种基于位交错结构的亚阈值10管SRAM单元,实现了电路在超低电压下能稳定地工作,并降低了电路功耗。采用内在读辅助技术消除了读干扰问题,有效提高了低压下的读稳定性。采用削弱单元反馈环路的写辅助技术,极大提高了写能力。该10管SRAM单元可消除半选干扰问题,提高位交错结构的抗软错误能力。在40 nm CMOS工艺下对电路进行了仿真。结果表明,该10管SRAM单元在低压下具有较高的读稳定性和优异的写能力。在0.4 V工作电压下,该10管SRAM单元的写裕度为传统6管单元的14.55倍。     

An Ultra-Low-Power Memory With a Subthreshold Power Supply Voltage

A 512$,times,$13 bit ultra-low-power subthreshold memory is fabricated on a 130-nm process technology. The fabricated memory is fully functional for read operation with a 190-mV power supply at 28 kHz, and 216 mV for write operation. Single bits are measured to read and write properly with$V _ DD$as low as 103 mV and 129 mV, respectively. The memory operates at a 1-MHz clock rate with a 310-mV power supply. This operating point has 1.197$muhboxW$power consumption, of which 0.366$muhboxW$is due to leakage and 0.831$muhboxW$is due to dynamic power dissipation. Analysis of the available fan-out or fan-in that can be supported at a given voltage is summarized. A number of circuit techniques are presented to overcome the substantially reduced on-to-off current ratios and the poor drive strength of transistors operating in subthreshold. These include a gated feedback memory cell, and hierarchical read and decode circuits. The memory is dynamic, with pseudo-static operation provided via self-timed control of the keeper transistors to mitigate increased variability manifested in subthreshold operation.     

Leakage Current Reduction Techniques for 7T SRAM Cell in 45 nm Technology

In this paper the impact of gate leakage on 7T static random access memory (SRAM) is described and three techniques for reducing gate leakage currents and sub threshold leakage currents are examined. In first technique, the supply voltage is decreased. In the second techniques the voltage of the ground node is increased. While in third technique the effective voltage across SRAM cell Vd = 0.348V and Vs = 0.234V are observed. In all the techniques the effective voltage across SRAM cell is decreased in stand-by mode using a dynamic self controllable voltage level (SVL) switch. Simulation results based on cadence tool for 45 nm technology show that the techniques in which supply voltage level is reduced is more efficient in reducing gate leakage than the one in which ground node voltage is increased. Result obtained show that 437 FA reductions in the leakage currents of 7T SRAM can be achieved.     

CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications

Wireless Personal Communications - This paper presents Carbon Nanotube FET (CNFET) based ultra-low-power Schmitt trigger SRAM designs which can operate at voltage levels as low as 200 mV, with high...     

基于CMOS阈值电压的基准电路设计

在数/模混合集成电路设计中电压基准是重要的模块之一.针对传统电路产生的基准电压易受电源电压和温度影响的缺点,提出一种新的设计方案,电路中不使用双极晶体管,利用PMOS和NMOS的阚值电压产生两个独立于电源电压和晶体管迁移率的负温度系数电压,通过将其相减抵消温度系数,从而得到任意大小的零温度系数基准电压值.该设计方案基于某公司0.5 μm CMOS工艺设计,经HSpice仿真验证表明,各项指标均已达到设计要求.     

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications

A novel single-ended boost-less 7T static random access memory cell with high write-ability and reduced read failure is proposed. Proposed 7T cell utilizes dynamic feedback cutting during write/read operation. The 7T also uses dynamic read decoupling during read operation to reduce the read disturb. Proposed 7T writes “1” through one NMOS and writes “0” using two NMOS pass transistors. The 7T has mean \((\mu )\) of 222.3 mV (74.1 % of supply voltage) for write trip point where 5T fails to write “1” at 300 mV. It gives mean \((\mu )\) of 276 mV (92 % of supply voltage) for read margin, while 5T fails due to read disturb at 300 mV. The hold static noise margin of 7T is maintained close to that of 5T. The read operation of 7T is 22.5 % faster than 5T and saves 10.8 % read power consumption. It saves 36.9 % read and 50 % write power consumption as compared to conventional 6T. The novel design of proposed 7T consumes least read power and achieves the lowest standard deviation as compared to other reported SRAM cells. The power consumption of 1 kb 7T SRAM array during read and write operations is 0.70\(\times \) and 0.65\(\times \), respectively, of 1 kb 6T array. The techniques used by the proposed 7T SRAM cell allow it to operate at ultra-low-voltage supply without any write assist in UMC 90 nm technology node. Future applications of the proposed 7T cell can potentially be in low-voltage, ultra-low-voltage and medium-frequency operations like neural signal processor, sub-threshold processor, wide-operating-range IA-32 processor, FFT core and low-voltage cache operation.     

Low-Power Cache Design Using 7T SRAM Cell

On-chip cache consumes a large percentage of the whole chip area and expected to increase in advanced technologies. Charging/discharging large bit lines capacitance represents a large portion of power consumption during a write operation. We propose a novel write mechanism which depends only on one of the two bit lines to perform a write operation. Therefore, the proposed 7T SRAM cell reduces the activity factor of discharging the bit line pair to perform a write operation. Experimental results using HSPICE simulation shows that the write power saving is at least 49%. Both read delay and static noise margin are maintained after carefully sizing the cell transistors     

5管SRAM单元的抗辐射性能研究

利用3D TCAD仿真,在45 nm 体硅工艺下,对5管SRAM单元和传统6管SRAM单元的抗辐射性能进行了对比研究。结果表明,5管SRAM单元的敏感面积更小,由该单元构成的SRAM阵列更难发生多位翻转。提出了一种带额外保护环的5管SRAM单元抗辐射加固策略,这种加固策略没有面积开销,模拟结果证实了该加固策略的有效性。     

一种基于阈值电压的新型基准电压源设计

SOC及智能功率集成电路对基准电压源提出了很高的要求。基于阈值电压和BiCMOS工艺,设计了一种新型的电流模式基准电压源。利用NMOS管阈值电压的线性负温度系数产生CTAT电压,与一种常见的PTAT电压相加,产生了对温度不敏感的基准电压。电路基于TSMC0.5μm BiCMOS工艺,采用Cadence Spectre对电路的各项性能进行了仿真验证。仿真结果表明,在宽温度范围(-40℃到120℃)内温度系数为9×10-6/℃,基准电压值为951mV。     

Statistical Design of the 6T SRAM Bit Cell

In this paper, a method for the statistical design of the static-random-access-memory bit cell is proposed to ensure a high memory yield while meeting design specifications for performance, stability, area, and leakage. The method generates the nominal design parameters, i.e., the widths and lengths of the bit-cell transistors, which provide maximum immunity to the variations in a transistor's dimensions and intrinsic threshold-voltage fluctuations. Moreover, the need to deviate from the conventional bit-cell sizing strategy to obtain a high-yield low-leakage design in the nanometer regime is demonstrated.      

EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement

Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a built in structure to extract this information is a very relevant choice to fast diagnose the failure in the memory. Thus, the objective of this paper is to present a built in self-diagnosis of EEPROM memory cells, based on threshold voltage extraction. In order to extract the threshold voltage, the modified circuit and the associated test sequence are presented. Based on the threshold voltage extraction, complementary information is proposed to improve the classical memory diagnosis methodology.This revised version was published online in March 2005 with corrections to the cover date.     

Leakage Reduction in 18 nm FinFET based 7T SRAM Cell using Self Controllable Voltage Level Technique

Wireless Personal Communications - As the technology is scaled the power consumption increases significantly, because of which the battery life of portable devices is reduced. Due to high power...     

基于阈值电压漂移的VDMOS寿命评价

随着DC/DC电源的快速发展,作为其中的开关管,VDMOS器件的可靠性一直受到关注.基于VDMOS阈值电压漂移的失效机理研究,对DC/DC电源上的VDMOS器件进行寿命评价;在135 ℃、150 ℃和165 ℃三种温度下进行加速老化试验,以阈值漂移量20 mV为失效判据,利用Arrhenius模型对试验结果进行分析,得到其失效激活能为1.18 eV,推算出其工作状态下的中位寿命特征值为4.0×105 h.分析认为,引起阈值电压漂移的原因主要是界面态电荷的积累.     

Design Considerations for PD/SOI SRAM: Impact of Gate Leakage and Threshold Voltage Variation

We present a critical study of the impact of gate tunneling currents on the yield of 65-nm partially depleted/silicon-on-insulator (PD/SOI) SRAM designs. A new gate leakage monitor structure is developed to obtain device-specific gate leakage characteristics of the SRAM cells. This allows us to explore the design space accurately with reliable process information at an early stage. By relying on supply voltage-dependent analysis, it is shown that the gate-leakage impact on the cell yield can be nonmonotonic and substantial even for nondefective devices. It is also shown that design optimizations such as increased operating voltages or shorter hierarchical bitline architecture can help alleviate the gate-leakage impact on yield. Mixture importance sampling is used to estimate yield in terms of cell writability and stability. Threshold voltage variations to model random fluctuation effects are extrapolated from hardware results.     

基于SRL结构的抗辐射SRAM单元设计

在空间辐射环境中,单粒子翻转(SEU)效应严重影响了SRAM的可靠性,对航天设备的正常运行构成极大的威胁。提出了一种基于自恢复逻辑(SRL)结构的新型抗辐射SRAM单元,该单元的存储结构由3个Muller C单元和2个反相器构成,并采用读写线路分开设计。单粒子效应模拟实验结果表明,该单元不仅在静态存储状态下对SEU效应具有免疫能力,在读写过程中对SEU效应同样具有免疫能力。     

一种全nMoS SOI晶体管4管静态存储器单元

提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管.存取管的沟道长度小于下拉管的沟道长度.由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑"1".存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的"读"操作.背栅反馈同时增强了SRAM单元的静态噪声容限(SNM).该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积.对SRAM单元的读写速度和功耗做了仿真和讨论.该SRAM单元可以工作在0.5V电源电压下.     

一种全nMOS SOI晶体管4管静态存储器单元

提出了一种新颖的无负载4管全部由nMOS管组成的随机静态存储器(SRAM)单元.该SRAM单元基于32nm绝缘体上硅(SOI)工艺结点,它包含有两个存取管和两个下拉管. 存取管的沟道长度小于下拉管的沟道长度. 由于小尺寸MOS管的短沟道效应,在关闭状态时存取管具有远大于下拉管的漏电流,从而使SRAM单元在保持状态下可以维持逻辑“1" . 存储节点的电压还被反馈到存取管的背栅上,使SRAM单元具有稳定的“读”操作. 背栅反馈同时增强了SRAM单元的静态噪声容限(SNM). 该单元比传统的6管SRAM单元和4管SRAM单元具有更小的面积. 对SRAM单元的读写速度和功耗做了仿真和讨论. 该SRAM单元可以工作在0.5V电源电压下.