A Novel Design Approach for Ternary Compressor Cells Based on CNTFETs

Using multiple-valued logic provides more information transmission over a signal line. So it could solve the binary logic circuits problems such as interconnections requirement. In this paper, a universal method for designing ternary 3-2 and 4-2 compressor cells based on carbon nanotube field-effect transistors (CNTFETs) is presented. The proposed circuits use unique properties of CNTFETs, such as adjustable threshold voltage by changing CNT diameter and ballistic carrier transportation. In both designs transmission gates, ternary decoder and standard ternary buffers with different threshold voltages are used. The proposed compressors receive three (for 3-2 compressor) or four (for 4-2 compressor) ternary digits, produce the summation of these digits and show the results in two ternary digits (Sum, Carry). For evaluation and simulation the proposed circuits, Synopsys HSPICE simulator with 32 nm compact model is used in different simulation conditions.     

Design of CNTFET-based 2-bit ternary ALU for nanoelectronics

This article presents a hardware-efficient design of 2-bit ternary arithmetic logic unit (ALU) using carbon nanotube field-effect transistors (CNTFETs) for nanoelectronics. The proposed structure introduces a ternary adder–subtractor functional module to optimise ALU architecture. The full adder–subtractor (FAS) cell uses nearly 72% less transistors than conventional architecture, which contains separate ternary cells for addition as well as subtraction. The presented ALU also minimises ternary function expressions with utilisation of binary gates for optimisation at the circuit level, thus attaining a simple design. Hspice simulations results demonstrate that the ALU ternary circuits achieve great improvement in terms of power delay product with respect to their CMOS counterpart at 32 nm.     

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field-effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.     

Design and process variation analysis of CNTFET-based ternary memory cells

Two novel ternary CNTFET-based SRAM cells are proposed in this paper. The first proposed CNTFET SRAM uses additional CNTFETs to sink the bit lines to ground; its operation is nearly independent of the ternary values. The second cell utilizes the traditional voltage controller (or supply) of a binary SRAM in a ternary SRAM; it consists of adding two CNTFETs to the first proposed cell. CNTFET features (such as sizing and density) and performance metrics (such as SNM and PDP) and write/read times are considered and assessed in detail. The impact of different features (such as chirality and CNT density) is also analyzed with respect to the operations of the memory cells. The effects of different process variations (such as lithography and density/number of CNTs) are extensively evaluated with respect to performance metrics. In nearly all cases, the proposed cells outperform existing CNTFET-based cells by showing a small standard deviation in the simulated memory circuits.     

A low-power and robust quaternary SRAM cell for nanoelectronics

This paper presents an efficient and low-power quaternary static random-access memory (SRAM) cell based on a new quaternary inverter. For implementation, carbon nanotube field-effect transistors (CNTFETs) are used. Stacked CNTFETs are appropriately used in the proposed design to achieve a considerably low static power dissipation. The proposed SRAM has a more significant static noise margin due to its single quaternary digit line, and it is appropriate for MVL SRAM design as there are more than two stable states. The simulation results using Synopsys HSPICE with 32 nm Stanford comprehensive CNTFET model demonstrate the correct and robust operation of the proposed designs even in the presence of major process variations. In addition, the proposed SRAM cell is applied in a 4?×?4 SRAM array structure to demonstrate the efficiency of the proposed SRAM. The results indicate that the proposed design significantly lowers the power consumption and provides comparable static noise margins compared to the other state-of-the-art CNTFET-based circuits.

     

A 4:1 Multiplexer using dual chirality CNTFET-based domino logic in nano-scale technology

ABSTRACT

This paper proposes a 4:1 Multiplexer (MUX) designed using proposed Dual Chirality High-Speed Noise Immune Domino Logic (DCHSNIDL) technique for designing lower delay noise immune domino logic circuits in Carbon Nanotube Field Effect Transistors (CNTFETs) technology. Dynamic power consumption, speed and noise immunity of the circuit are improved by changing the threshold voltage of the CNTFETs. The chirality indices of the carbon nanotubes (CNTs) are varied to change the threshold voltage of the CNTFETs. Simulations are carried out for 32 nm Stanford CNTFET model in HSPICE for 2-, 4-, 8- and 16-input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9V. The proposed DCHSNIDL domino circuit reduces power consumption by a maximum of 61.77% and propagation delay by a maximum of 55.11% compared to Current-Mirror Based Process Variation Tolerant (CPVT) circuit in CNTFET technology. The proposed CNTFET-based domino technique shows a maximum reduction of 96.31% in power consumption compared to its equivalent circuit in CMOS technology for a 4-input OR gate. The proposed technique shows an improvement of 1.04× to 1.35× times in Unity Noise Gain (UNG) compared to various existing techniques in CNTFET technology. The 4:1 MUX designed using proposed technique has 48.91% lower propagation delay and consumes 52.80% lower power compared to MUX using CPVT technique.     

A Novel CNTFET-based Ternary Full Adder

The Full Adder is one of the most important and basic units of mathematic circuits that is the basic structure of many complex systems. Moreover, serial and serial-parallel mathematic processes can be carried out faster and more operative error-detection and error-correction codes can be employed in ternary logic implementations. In this work, we presented a new high-performance Ternary Full Adder (TFA) based on Carbon Nanotube Field-Effect Transistor (CNTFET) technology. The proposed design is well-matched with the Carbon Nanotube Field-effect Transistor knowledge and ternary logic value. The presented structure reduces the delay of the Ternary Full Adder and has high driving capability. The proposed Ternary Full Adder is simulated at varying supply voltages and temperatures using different frequencies by the Synopsys HSPICE circuit simulator. Simulation results determine improvement in terms of delay and Power-Delay Product (PDP) in comparison with the state-of-the-art designs. Simulations show that the proposed Ternary Full Adder cell shows approximately more than 53 % improvement in PDP compared to its counterparts.     

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Novel direct designs for 3-input exclusive-OR (XOR) function at transistor level are proposed in this article. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. Neither complementary inputs, nor V _DD and ground exist in the basic structure of these designs. The proposed designs have low dynamic and short-circuit power consumptions and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. Some effective approaches are presented for improving the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. All of the proposed designs and several classical and state-of-the-art 3-input XOR circuits are simulated in a realistic condition using HSPICE with 90 nm CMOS technology at six supply voltages, ranging from 1.3 V down to 0.8 V. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.     

An efficient reliability estimation method for CNTFET-based logic circuits

Carbon nanotube field-effect transistors (CNTFETs) have been widely studied as a promising technology to be included in post-complementary metal-oxide-semiconductor integrated circuits. Despite significant advantages in terms of delay and power dissipation, the fabrication process for CNTFETs is plagued by fault occurrences. Therefore, developing a fast and accurate method for estimating the reliability of CNTFET-based digital circuits was the main goal of this study. In the proposed method, effects related to faults that occur in a gate's transistors are first represented as a probability transfer matrix. Next, the target circuit's graph is traversed in topological order and the reliabilities of the circuit's gates are computed. The accuracy of this method (less than 3% reliability estimation error) was verified through various simulations on the ISCAS 85 benchmark circuits. The proposed method outperforms previous methods in terms of both accuracy and computational complexity.     

Novel and general carbon nanotube FET-based circuit designs to implement all of the 3 ternary functions without mathematical operations

In this paper, we propose new universal designs of ternary-valued logic (TVL) with high-speed, low-power and full swing output using carbon nanotube FETs (CNTFETs). All of the TVL functions (3⁹ functions) can be implemented in these designs. Ternary value logic is a promising alternative to binary logic due to the reduced integrated circuit (IC) interconnects and chip area. Therefore, a universal design of TVL is a good direction for the future of FPGA design using CNTFET. In this paper, new universal designs of ternary-valued logic based on CNTFETs are proposed and compared with the existing resistive-load CNTFET universal TVL designs. Extensive simulations have been performed in HSPICE to investigate the distribution of power consumption and the delay of the CNTFET-based universal cells due to variations in the supply voltage, the diameter of the CNT, and the room temperature. Simulation results show that the proposed universal TVL designs result in significantly lower power consumption and delay compared with previous resistive-load CNTFET universal TVL implementations.     

Low power FGMOS-based four-quadrant current multiplier circuits

In this paper, low-power, high-speed four-quadrant analog multiplier circuits have been presented, based on simple current squarer circuits. The squarer circuits consist of a floating-gate MOS transistor, operating in saturation region plus a resistor. These multipliers have a unique property of greatly reduced power as they do not have any bias currents. For performance evaluation, the designs are simulated using HSPICE software in 0.18 µm (level-49 parameters) TSMC CMOS technology. Using ± 0.5 V DC supply voltages for the first design, the simulation resulted in a maximum linearity error of 0.8%, the ? 3 dB bandwidth of 635 MHz, the Total Harmonic Distortion of 0.57% (at 1 MHz), and maximum and static power consumption of 40.4 and 5.75 µW, respectively. Corresponding values for the second design with 1 V DC supply voltage are 0.4%, 394.8 MHz, 0.72%, 44 and 11.4 µW, respectively. Furthermore, in order to verify the robustness and reliability of the proposed works, Monte Carlo analysis are performed. For the mentioned analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are considered.     

Ultra-low-power carbon nanotube FET-based quaternary logic gates

This paper presents low-power carbon nanotube field-effect transistor (CNTFET)-based quaternary logic circuits. The proposed quaternary circuits are designed based on the CNTFET unique properties, such as the same carrier mobility for N- and P-type devices and also providing desirable threshold voltages by adopting proper diameters for the nanotubes. In addition, no paths exist between supply and ground rails in the steady states of the proposed designs, which eliminates the ON state static current and also the stacking technique is utilised in order to significantly reduce the leakage currents. The results of the simulations, conducted using Synopsys HSPICE with the standard 32 nm CNTFET technology, confirm the significantly lower power consumption, higher energy efficiency and lower sensitivity to process variation of the proposed designs compared to the state-of-the-art quaternary logic circuits. The proposed quaternary logic circuits have on average 92, 99 and 91% less total power, static power and PDP, respectively, compared with the most low-power and energy-efficient CNTFET-based quaternary logic circuits, recently presented in the literature.     

A New Capacitance-to-Frequency Converter for On-Chip Capacitance Measurement and Calibration in CMOS Technology

In this paper, a new capacitance-to-frequency converter using a charge-based capacitance measurement (CBCM) circuit is proposed for on-chip capacitance measurement and calibration. As compared to conventional capacitor measurement circuits, the proposed technique is able to represent the capacitance in term of the frequency so that the variations can be easily handled in measurement or calibration circuits. Due to its simplicity, the proposed technique is able to achieve high accuracy and flexibility with small silicon area. Designed using standard 180 nm CMOS technology, the core circuit occupies less than 50 μm × 50 μm while consuming less than 60 μW at an input frequency of 10 MHz. Post-layout simulation shows that the circuit exhibits less than 3 % measurement errors for fF to pF capacitances while the functionality has been significantly improved.     

Efficient radix-r adders for nanoelectronics

In this study, a new design method and efficient designs for radix-r adders are proposed for carbon nanotube field effect transistor (CNFET) FET nanotechnology. This application also investigates the capability of the nanoscale device for designing high-performance analogue circuits. The proposed designs benefit from the unique electrical properties of CNFET, such as near-ideal current voltage characteristics, very high transconductance, high-performance switches and very high-performance and high-gain binary inverters, at nanoscale. Moreover, adjustable threshold voltage and the same mobility of electrons and holes in a CNFET facilitate the design and modification procedures. The proposed design can be considered as an instance of a general adder, capable of adding radix-r digits with high precision. It is noteworthy that a very limited number of carbon nanotube diameters for designing the proposed adder are needed, which enhance the manufacturability. The proposed circuits are designed based on arithmetic relations and are also verified at 32 nm feature size using HSPICE and the Stanford standard SPICE model.     

Diagnostics of Analog Circuits Based on LS-SVM Using Time-Domain Features

Most researchers use wavelet transforms to extract features from a time-domain transient response from analog circuits to train classifiers such as neural networks (NNs) and support vector machines (SVMs) for analog circuit diagnostics. In this paper, we have proposed some new feature selection methods from a time-domain transient response, and compared the diagnostic results based on a least squares SVM (LS-SVM) using different time-domain feature vectors. First, we have improved two traditional feature selection methods: (a) using the mean and standard deviation in wavelet transform features, and (b) using the mean, standard deviation, skewness, kurtosis, and entropy in statistical property features. Then, a conventional time-domain feature vector based on the impulse response properties of a control system has been proposed. The simulation experiments for a leapfrog filter and a nonlinear rectifier show that: (1) the two improved methods have better accuracy than the traditional methods; (2) the proposed conventional time-domain feature vector is effective in the diagnostics of analog circuits—over 99 % for both of the two example circuits; (3) the proposed diagnostic method can diagnose soft faults, hard faults, and multi-faults, regardless of component tolerances and nonlinearity effects.     

Three novel single-stage full swing 3-input XOR

In this paper, three novel designs for single-stage, 3-input XOR logic cells are proposed. The design uses either Transmission Gate (TG) or Pass Transistor (PT) on similar topologies. The proposed circuits are area and power efficient because minimum-sized transistors are used in ratioless realisations. At the output, the designs give strong logic-levels. The topologies have minimised delay because the critical path consists of only three minimum-sized transistors. The delay estimation is presented. The circuits are simple and layouts are easy to build. Further, rail-to-rail voltage-swing at the output ensures good driving capability even at low voltages and at high frequencies ranging up to 10 GHz with minimum transistor count. The proposed designs and other existing candidate designs are simulated in a pragmatic condition on Cadence 90 nm CMOS technology at various supply voltages ranging from +0.8 V to +1.2 V. The simulation results illustrate that the proposed designs have comparable delay time to most candidate designs while it outperform all of them on total power consumption and PDP. As expected, the TG-based design reports best performance while the PT-based design follow as closed second with better component economy and control input overload. An application of the proposed XORs in ripple carry adders confirms the functionality of the cells in circuit implementation.     

Sub-1 V band-gap based and MOS threshold-voltage based voltage references in 0.13 µm CMOS

Portable and implantable device applications require low supply voltage reference circuits due to increasing trend for lower power requirements. Voltage references have been proposed for operation below 1 V for CMOS and a comprehensive analysis of the behavior of the different topologies is needed for ultra-low power designs, in order to select the right circuit topology for a given requirement. This work compares two major classes of voltage reference topologies: threshold voltage (V_T0)-based and (V_G0) bandgap voltage-based reference circuits. Four different topologies of voltage-reference designs with 1-V supply were designed and fabricated in 130 nm CMOS process. Monte Carlo analysis shows the variability of the references and of their temperature coefficients (TC), and the results are compared to measured samples. Simulations and measurements show that the threshold voltage-based references are more susceptible to the variations in the CMOS fabrication process.     

Band notched UWB circular monopole antenna with inductance enhanced modified mushroom EBG structures

Circular monopole antenna for ultra-wide band applications with notch band transition from WLAN to WiMAX is presented. The proposed antenna rejects WiMAX band (3.3–3.8 GHz). Antennas utilises modified mushroom-type electromagnetic band gap (EBG) structures to achieve band-notched designs. The proposed inductance enhanced modified EBG structures are 34 % compact than the conventional mushroom EBG structures. The band notched antenna designs using EBG structures have advantages like notch-frequency tuning, antenna design independent approach and omnidirectional radiation pattern. The step wise effect of inductance enhancement and tuning of notch from WLAN band (5–6 GHz) to WiMAX band is shown. Effect of variation of EBG structure parameters on which notched frequency depends is investigated. The proposed antenna has been fabricated on low cost FR4 substrate with overall dimensions as (42 × 50 × 1.6) mm³. Measured results are in good agreement with simulated ones.     

Blind Deconvolution of Multi-Input Single-Output Systems With Binary Sources

The problem of blind source separation for multi-input single-output (MISO) systems with binary inputs is treated in this paper. Our approach exploits the constellation properties of the successor values for each output sample. In the absence of noise, the successors of each output value form a characteristic finite set of clusters (successor constellation). The shape of this constellation is invariant of the predecessor value and it only depends on the last filter tap. Consequently, the localization of the successors constellation can lead to the removal of the last filter tap, thus reducing the length of the filter—a process we call channel deflation. Based on the successor observation clustering (SOC), we develop two algorithms for blind source separation—SOC-1 and SOC-2—differing mainly on the required size of the data set. Furthermore, the treatment of the system in the presence of noise is described using data clustering and data correction. The problem of noise is attacked using a statistical-mode-based method. Moreover, we correct the problem of misclassified observations using an iterative scheme based on the Viterbi algorithm for the decoding of a hidden Markov model (HMM).     

Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.