Performance of Quantized Turbo Decoding for Decoders with Maximum a Postriori Algorithm

This paper investigates Bit Error Performance for quantized turbo code over Gaussian channels. The turbo encoder is built using a parallel concatenation of two recursive systematic convolution encoders and a random interleaver. The turbo decoder employs' two iterative symbol by symbol MAP based algorithm decoders for decoding the received data. For a given quantization level, the Bit Error Rates are examined by considering the influence of the code structure, the block size, and the number of decoding steps. Finally, to measure loss of power efficiency due to quantization, the results are compared to previously published results for the unquantized case under the same Bit to noise ratio and the code structure. Omar M. Hasan Was born in Amman, Jordan, in 1964. He received the MS and the Ph.D degrees in Communications Engineering from New Mexico State University, Las Cruces, New Mexico, USA, in 1990 and 1996. Currently, he is the chairman of the Communications Engineering department at Princess Sumaya University in Amman, Jordan. During 1991–1992, he works at the RF and the digital system divisions at the Physical Science Laboratory, Las Cruces, New Mexico. During 1996, he worked as a researcher at the Manuel Lujan, Jr. Center for Space Telemetering and Telecommunications. Las Cruces, New Mexico, USA. During the year 2000, he was the head of research and development group at Cardiac Teleccommunications, Webster, TX, USA. His main research interests include turbo coding, narrow-band FSK systems, telemedicince, and mobile aided learning.     

Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder

Iterative decoding of convolutional turbo code (CTC) has a large memory power consumption. To reduce the power consumption of the state metrics cache (SMC), low-power memory-reduced traceback maximum a posteriori algorithm (MAP) decoding is proposed. Instead of storing all state metrics, the traceback MAP decoding reduces the size of the SMC by accessing difference metrics. The proposed traceback computation requires no complicated reversion checker, path selection, and reversion flag cache. For double-binary (DB) MAP decoding, radix-2 $,times,$2 and radix-4 traceback structures are introduced to provide a tradeoff between power consumption and operating frequency. These two traceback structures achieve an around 20% power reduction of the SMC, and around 7% power reduction of the DB MAP decoders. In addition, a high-throughput 12-mode WiMAX CTC decoder applying the proposed radix-2$,times,$2 traceback structure is implemented by using a 0.13-$mu$m CMOS process in a core area of 7.16 mm$^{2}$. Based on postlayout simulation results, the proposed decoder achieves a maximum throughput rate of 115.4 Mbps and an energy efficiency of 0.43 nJ/bit per iteration.      

一种Turbo码高速并行译码算法

针对Turbo码MAP译码算法运算量、存储量大和译码延时长的问题,基于双滑动窗的基本思想,提出一种高速并行的译码算法。计算机仿真表明,该算法是存储量与译码性能的良好折衷。     

Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms

Maximum A Posteriori (MAP) decoding is a crucial enabler of turbo coding and other powerful feedback-based algorithms. To allow pervasive use of these techniques in resources constrained systems, it is important to limit their implementation complexity, without sacrificing the superior performance they are known for. We show that introducing traceback information into the MAP algorithm, thereby leveraging components that are also part of Soft-Output Viterbi Algorithms (SOVA), offers two unique possibilities to simplify the computational requirements. Our proposed enhancements are effective at each individual decoding iteration and therefore provide gains on top of existing techniques such as early termination and memory optimizations. Based on these enhancements, we will present three new architectural variants for the decoder. Each one of these may be preferable depending on the decoder memory hardware requirements and number of trellis states. Computational complexity is reduced significantly, without incurring significant performance penalty.

Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders

Turbo decoders inherently require large hardware for VLSI implementation as a large amount of memory is required to store incoming data and intermediate computation results. Design of highly efficient Turbo decoders requires reduction of hardware size and power consumption. In this paper, finite precision effects on the performance of Turbo decoders are analyzed and the optimal word lengths of variables are determined considering tradeoffs between the performance and the hardware cost. It is shown that the performance degradation from the infinite precision is negligible if 4 bits are used for received bits and 6 bits for the extrinsic information. The state metrics normalization method suitable for Turbo decoders is also discussed. This method requires small amount of hardware and its speed does not depend on the number of states. Furthermore, we propose a novel adaptive decoding approach which does not lead to performance degradation and is suitable for VLSI implementation.     

低复杂度Turbo码译码并行实现

MAX-LOG-MAP是Turbo码译码算法的简化算法,本文提出了该算法的并行阵列集成电路实现结构,给出阵列的数据流向和译码算法在阵列中的计算过程,分析了阵列结点联接关系和数据存贮结构,以及数据运算之间的简单时序关系.通过计算机仿真,证明了这种并行实现结构的正确性.     

Turbo码的一种并行译码方案及相应的并行结构交织器研究

Turbo码基于MAP算法译码的递推计算所引入高的译码延迟限制了Turbo码在高速率数据传输中的应用。为了解决这个问题,该文提供了一种降低译码延迟的并行译码方法。并行处理方案的实现必须通过适当的交织以避免两个译码器对外信息读写的数据冲突。该文在分析了任意无冲突交织方式可能性的存在之后,给出了设计任意地适用于并行处理方案的S随机交织器的方法。仿真验证了并行译码方案的误比特性能。     

一种短时延的Turbo码并行译码算法

由于迭代译码是Turbo码译码的主要特点,因而在译码的过程中会带来很大的时延.为了减小译码延时,本文将整块译码器分成w个子块,并且运用计算复杂度低的T-BCJR算法,在相邻的子块译码器之间相互运用边界分配值作为下一次迭代的初始值,而不是采用各相邻的子块之间重叠部分进行译码,故使译码延时下降为原来的1/w。     

A Modified max-log-MAP Decoding Algorithm for Turbo Decoding

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Turbo码并行译码中无冲突交织器设计方案

交织器的结构可以影响到Turbo码的最小码距,进而影响其编码增益,最终对误比特率产生较大影响。交织器的主要功能就是随机化输入信息码序列,并让两个子编码模块在任何时刻,不会同时输出码重较轻的码字。交织器的随机性直接影响着Turbo码并行译码性能,针对现有无冲突交织器中随机性较小的特点,引入行内、行间交织等处理方式,进一步增加了交织表的随机性,以此提高Turbo码并行译码的性能,并给出了行内、行间交织设计实例。     

基于CUDA的双二进制Turbo码并行译码方法

卫星回传信道数字视频广播(Digital Video Broadcasting-Return Channel over Satellite,DVB-RCS)标准中回传信道采用双二进制Turbo码作为前向纠错编码(Forwar Error Correctiong,FEC),为了提升译码算法的运算速度,在Max-LogMAP译码算法基础上,提出了基于统一计算设备架构(Compute Unified Device Architecture,CUDA)的图形处理器(Graphic Processing Unit,GPU)并行计算加速译码方法,其运算速度与中央处理器(Central Processing Unit,CPU)运行相比,提高了约20倍。     

High-Speed Recursion Architectures for MAP-Based Turbo Decoders

The maximum a posterior probability (MAP) algorithm has been widely used in Turbo decoding for its outstanding performance. However, it is very challenging to design high-speed MAP decoders because of inherent recursive computations. This paper presents two novel high-speed recursion architectures for MAP-based Turbo decoders. Algorithmic transformation, approximation, and architectural optimization are incorporated in the proposed designs to reduce the critical path. Simulations show that neither of the proposed designs has observable decoding performance loss compared to the true MAP algorithm when applied in Turbo decoding. Synthesis results show that the proposed Radix-2 recursion architecture can achieve comparable processing speed to that of the state-of-the-art recursion (Radix-4) architecture with significantly lower complexity while the proposed Radix-4 architecture is 32% faster than the best existing design     

Generic Direct Approach for Decoding Turbo Codes Using Probability Density Based Reliability Model

Journal of Communications Technology and Electronics - The probability of the received bit values has been directly used in the performance enhanced reliability based direct decoding algorithm for...     

A High-Throughput Maximum a Posteriori Probability Detector

This paper presents a maximum a posteriori probability (MAP) detector, based on a forward-only algorithm that can achieve high throughputs. The MAP algorithm is optimal in terms of bit error rate (BER) performance and, with Turbo processing, can approach performance close to the channel capacity limit. The implementation benefits from optimizations performed at both algorithm and circuit level. The proposed detector utilizes a deep-pipelined architecture implemented in skew-tolerant domino and experimentally measured results verify the detector can achieve throughputs greater than 750 Mb/s while consuming 2.4 W. The 16-state EEPR4 channel detector is implemented in a 0.13$ mu{hbox {m}}$ CMOS technology and has a core area of 7.1 ${hbox {mm}}^{2}$.      

Turbo码解码过程中的加权算法

本文通过调整迭代解码过程中系统位接收值的加权系数,提出了一种Turbo码加权迭代解码算法。该算法改变了迭代运算后Turbo码解码器输出软值中系统位接收值信息和它的外部估计信息的比重,使Turbo码无论在低信噪比或是在高信噪比时均具有优良的纠错性能。仿真结果显示,采用Turbo码加权迭代解码算法,不仅能提高Turbo码的收敛速度,而且能进一步降低Turbo码解码时的地板值,使Turbo码的比特误码率在高、低信噪比时都能够得到进一步改善。     

一种高效的Turbo码硬件实现算法

针对Turbo码译码实现中硬件消耗、时延和纠错性能之间的矛盾,对Turbo码硬件实现中的译码算法进行了优化研究,提出了一种基于MAX-Log-MAP算法的高效Turbo码硬件实现算法。实验表明,本文所实现的Turbo码是硬件消耗与译码性能的良好折衷。     

Turbo码译码算法的迭代准则

仿真分析了迭代次数对Turbo编码性能的影响,包括对误比特率(BER)和误帧率(FER)的影响.并通过对附加信息的距离变化进行度量,提出了一种新的迭代停止判断准则,这种准则能动态地选择迭代次数.     

Turbo Code译码方法的改进

在文章中，首先介绍Turbo码的基本编译码结构和它的译码算法MAP。在此基础上，尝试对MAP算法的循环译码的后向递推的起点以及循环译码结构的最终判决条件根据实际应用情况进行改进。将译码的后向递推的起点定义为译码的前向递推的终点，并且将每一轮译码结果进行加权相加，得到最后系统输出。最后，根据MATLAB仿真的结果论证改进后的算法能减少系统的误码率。     

Turbo码概率-代数联合解码算法

Turbo码采用修正的BAHL et al.算法实现解码.这是一种基于软值的概率迭代解码算法.本文在保持Turbo码迭代软解码算法优点的基础上,充分利用Turbo码编码器结构这一确知条件,结合代数解码原理,提出了一种Turbo码概率-代数联合解码算法.该算法结合了概率解码和代数解码的优点,又有效避免了误差传播的发生,使Turbo码的纠错性能在原经典算法的基础上得到进一步的提高.该算法不仅为降低Turbo码的比特误码率和误差地板值提供了一种新的研究途径,而且因其更好的纠错性能而具有十分明显的实用价值.仿真实验结果显示,在比特误码率(BER)为10^-3~10^-4时,与经典Turbo码解码算法相比,采用该算法能获得0.1dB左右的编码增益.