AlGaAs/GaAs HBT IC's for high-speed lightwave transmission systems

The implementation of multigigabit-per-second optical communication systems requires many high-speed electronic circuit components that meet stringent performance requirements. Several important research prototype circuits for fiber-optic transmission, implemented in a baseline AlGaAs/GaAs HBT process, are discussed. These include a 20 Gb/s decision circuit, a 27 Gb/s 1:2 demultiplexer, a 30 GB/s 2:1 multiplexer, a 27 Gb/s 4:1 multiplexer, and a 11 Gb/s laser driver IC     

High-speed 8:1 multiplexer and 1:8 demultiplexer implemented withAlGaAs/GaAs HBTs

An 8:1 multiplexer (MUX) and 1:8 demultiplexer (DMUX) implemented with AlGaAs/GaAs heterojunction bipolar transistors are described. The circuits were designed for lightwave communications, and were demonstrated to operate at data rates above 6 Gb/s. These are among the fastest 8-b MUX-DMUX circuits ever reported. Each contains about 600 transistors and consumes about 1.5 W. The pair provides features such as resettable timing, data framing, and clock recovery circuitry, and a built-in decision circuit on the DMUX. Emitter-coupled logic (ECL) compatible input/output (1/O) signals are available. The circuits were implemented with bi-level current mode logic (CML) and require a -5.2-V power supply and a +1-V bias for ECL compatibility     

InP DHBT technology and design methodology for high-bit-rateoptical communications circuits

High-bit-rate optical communication links require high performance circuits. Electrical time division multiplex (ETDM) single channel bit-rate of 40 Gb/s is at hand, due to recent progress in both technology and design methodology. Multilevel modulation format can be envisaged for ETDM transmission. An InP double heterojunction bipolar transistor technology is presented in this paper. The methodology used and tools developed with optical communications in mind are also discussed. Fabricated circuits are reported: 40 Gb/s multiplexer and demultiplexer, a 20 Gb/s driver, a 30 Gb/s selector-driver, a 22 Gb/s decision circuit, and a decision-decoding circuit for multilevel transmissions     

8 Gb/s 8:1 multiplexer and 1:8 demultiplexer IC's using GaAs DCFLcircuit

High-speed 8:1 multiplexer and 1:8 demultiplexer ICs composed of GaAs direct-coupled FET logic (DCFL) have been designed and fabricated. The ICs were designed with a tree-type architecture and using memory-cell-type flip-flops (MCFFs). Self-aligned GaAs MESFETs with a gate length of 0.5 μm were used in these ICs. The propagation delay time of the DCFL inverter was 19.0 ps/gate. Both ICs operated up to 8 Gb/s with power dissipations of 1.5 W for the multiplexer and 1.9 W for the demultiplexer at a single power supply voltage of 2.0 V. These ICs are applicable for multigigabit lightwave communication systems     

50-Gb/s SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer for serial communication systems

4:1 multiplexer and 1:4 demultiplexer ICs targeting SONET OC-768 applications are reported. The ICs have been implemented using a 120-GHz-f/sub T/ 0.18-/spl mu/m SiGe BiCMOS process. Both ICs have been packaged to enable bit error rate testing by connecting their serial interfaces. Error-free operation has been achieved for both circuits at data rates beyond 50 Gb/s. At a -3.6-V supply voltage, the multiplexer and demultiplexer dissipate 410 and 430 mA, respectively. Switching behavior of the 4:1 multiplexer has also been checked up to 70 Gb/s.     

Challenges in the Cell-Based Design of Very-High-Speed SiGe-Bipolar ICs at 100 Gb/s

A cell-based design concept for the efficient design of higher integrated SiGe-bipolar circuits operating at data rates equal to or greater than 100 Gb/s is proposed. The performance limitations of circuit designs at these high data rates are discussed with special regard to associated cell-based design aspects. The performances of two cell-based designs are demonstrated by a 100 Gb/s 2:1 multiplexer IC and a 100 Gb/s 1:2 demultiplexer IC with on-chip clock- and data-recovery.      

10 Gb/s silicon bipolar 8:1 multiplexer and 1:8 demultiplexer

High-speed multiplexer and demultiplexer circuits are key components in high-speed optical communication systems such as SONET. As optical communication link speeds increase, faster electronic interface circuitry is required. The use of multiplexer circuits allows most of the electronic circuitry to operate on parallel data at a lower speed, reducing the speed requirements of much of the system. A retimed 8:1 multiplexer and a 1:8 demultiplexer which operate at 10 Gb/s are described. These circuits were fabricated in high-speed silicon bipolar process. Design optimization techniques were used to achieve maximum performance. The retimed multiplexer and the demultiplexer dissipate 3.8 and 4.3 W, respectively     

基于锗硅工艺的40-Gb/s分接器

采用0.35μmSiGeBiCMOS工艺设计了一个1∶2分接器,核心电路单元采用经过改进的电路结构实现。由于传统的发射极耦合逻辑结构(ECL)电路的工作速度不能达到要求,对此加以了改进,在发射极耦合逻辑结构中增加一级射极跟随器,形成发射极-发射极耦合逻辑(E2CL)结构,从而提高电路的工作速度。测试结果显示,所设计分接器的工作速度可以达到40Gb/s。整个电路采用单电源5V供电,功耗为510mW。     

2.488 Gb/s SONET multiplexer/demultiplexer with frame detectioncapability

The authors describe a novel scheme that allows a demultiplexer, a byte aligner, and a frame detection circuit tube to be integrated on one chip without compromising the demultiplexer's performance. A research prototype integrated circuit (IC) that incorporates this scheme was designed to operate at speeds up to the SONET STS-48 (synchronous transport signal level 48) rate of 2.488 Gb/s. The IC is implemented in GaAs enhancement/depletion mode MESFET technology, and it performs 1:8 demultiplexing, byte alignment, and SONET frame detection functions. A separate IC that performs 8:1 multiplexing was also implemented using the same technology. The bit error rate; test results show that the multiplexer and demultiplexer with frame detector can operate at 2.488 Gb/s with a bit error rate less than 1×10^-14. Both ICs were tested at data rates up to 3 Gb/s     

Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optictransmission

We report a new integrated circuit for multiplexing and demultiplexing at rates of 100 Gb/s. In transistor multiplexer/demultiplexer circuits, the operating data rate is limited by transistor bandwidth. The demonstrated circuit, which uses terahertz Schottky diodes, readily attains the necessary bandwidths. The IC, based in the diode nonlinear-transmission line (NLTL) technology, consists of an array of four sample-hold gates driven by NLTL strobe generators. To permit use in multiplexing, the sample-hold gates use a six-diode configuration with 150 GHz output bandwidth. Initial measurements with simple data patterns at 104 Gb/s are demonstrated     

5-Gbit/s Si integrated regenerative demultiplexer and decision circuit

A silicon bipolar circuit is presented which may be used as either a 1:2 demultiplexer or a decision circuit up to the bit rate of 5 Gb/s. The circuit was fabricated with a standard bipolar technology with oxide-wall isolation, 2-/spl mu/m emitter stripe widths, and a transit frequency of about 9 GHz at V/SUB CE/=1 V. The high-speed performance of the circuit was achieved by applying a double sampling scheme. Clock phase margin (CPM) and decision ambiguity are 120/spl deg/ and 150 mV at 4 Gb/s, respectively. CPM at 5 Gbit/s is about 90%. Decision feedback equalization may be included in the circuit scheme for optional use.     

A 1.8 Gb/s GaAs optoelectronic universal switch LSI withmonolithically integrated photodetector and laser driver

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8 Gb/s optical-input/optical-output four-channel time-division switch, a 1.8 Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0 Gb/s electrical-output 4:1 multiplexer, and a 2.8 Gb/s electrical-input/electrical-output 4×4 space-division switch. It uses a new multistage 2×2 switch block with small hardware and high-speed operation. It can be expanded to a 16×16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN     

Phase and amplitude pre-emphasis techniques for low-power serial links

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s.     

Ultrahigh-speed heterojunction bipolar transistormultiplexer/demultiplexer ICs

High-speed 2-b monolithic integrated multiplexer (MUX) and demultiplexer (DMUX) circuits have been developed using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs) with improved high-speed performance. Both ICs were designed using emitter-coupled logic. The 2:1 MUX was composed of a D-type flip-flop (D-FF) merging a selector gate and a T-type flip-flop (T-FF). The 1:2 DMUX consisted of two D-FFs driven at a clock of half the rate of the input data. Error-free operation with a pseudorandom pattern was confirmed up to 10 Gb/s. The rise and fall times of the output signals of both ICs were 40 and 25 ps, respectively. HBT frequency dividers were used as inputs for both ICs in order to find the maximum operation speed. Although only a few test patterns were available, the maximum operation speeds of the MUX and DMUX were found to be around 15 and 19 Gb/s, respectively     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

40-Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120-nm standard CMOS

We present an integrated 2:1 multiplexer and a companion 1:2 demultiplexer in CMOS. Both integrated circuits (ICs) operate up to a bit rate of 40 Gb/s. The 2:1 multiplexer features two in-phase data inputs which are achieved by a master-slave flip-flop and a master-slave-master flip-flop. Current-mode logic is used because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. The multiplexer uses no output buffer and directly drives the 50-/spl Omega/ environment. An inductance connected in series to the output in combination with shunt peaking is used to enhance the bandwidth of the multiplexer. Fully symmetric on-chip inductors are used for peaking. The inductors are mutually coupled to save chip area. Lumped equivalent models of both peaking inductors allow optimization of the circuit. The ICs are fabricated in a 120-nm standard CMOS technology and use 1.5-V supply voltage. Measured eye diagrams of both ICs demonstrate their performance.     

Silicon bipolar integrated circuits for multi-Gb/second opticalcommunication systems

The authors discuss several important circuits for fiber-optic transmission, implemented in an advanced silicon bipolar integrated circuit technology. Specifically, the authors discuss the design considerations and measured performance of a 2:1 multiplexer, front end receiver, limiting amplifier, and decision circuit IC. Also discussed are three hybrid circuit modules: a 2:1 multiplexer, 1:2 demultiplexer, and parallel processing decision circuit. These ICs and hybrid circuit modules operate at multi-Gb/s data rates. The performance of these ICs indicates that advanced silicon bipolar integrated circuits with their high speed, functionality and low cost potential could play an important role in alleviating the electronic bottleneck in future multigigabit optical communication systems     

High-speed Si-bipolar IC design for multi-Gb/s optical receivers

The authors developed several special circuits to minimize the decrease in speed caused by parasitics. The common-base circuit assures flat and wide frequency preamplifier response even when V_ee is unstable because of bond wire inductance. Cascode interconnections between circuit blocks prevent waveform degradation due to line capacitance discharge. The high level of integration prevents the signal speed from decreasing due to chip interfaces and external interference. Using these circuits and Si-bipolar ESPER (emitter-base self-aligned structure with polysilicon electrodes and resistors) transistors whose f_T was 28 GHz, the authors fabricated three ICs: a preamplifier with a 5.1 GHz bandwidth, a fully integrated automatic gain control (AGC) amplifier with a 3.6 GHz bandwidth, and a decision circuit that operates at 10.6 Gb/s. The authors used these ICs and an avalanche photodiode (APD) to construct a 5 Gb/s optical receiver with a minimum detectable optical power of -26.8 dBm. The speed of the Si ICs exceeded 5 Gb/s     

SiGe-HBT-based 54-gb/s 4:1 multiplexer IC with full-rate clock for serial communication systems

A 4:1 multiplexer (MUX) IC for 40 Gb/s and above operations in optical fiber link systems has been developed. The ICs are based on 122-GHz-f/sub T/ 0.2-/spl mu/m self-aligned selective-epitaxial-growth SiGe HBT technology. To reduce output jitter caused by clock duty distortion, a master-slave delayed flip-flop (MS-DFF) with full-rate clock for data retiming is used at the final stage of the MUX IC. In the timing design of the critical circuit for full-rate clocking, robust timing design that has a wide timing margin between data and clock at the MS-DFF was achieved. Measurements using on-wafer probes showed that the MUX attained 54-Gb/s operation with an output voltage-swing of 400 mVpp. The output rms jitter generated by the MUX was 0.91 ps and tr/tf (10%-90%) was 11.4/11.3 ps at a data rate of 50 Gb/s. Power consumption of the IC was 2.95 W at a power supply of -4.8 V. Error-free operation (<10/sup -12/) in back-to-back configuration of the MUX and a 1:4 DEMUX IC module at a data rate of 45 Gb/s was confirmed. We therefore concluded that the MUX IC can be applied for transmitter functions in optical-fiber-link systems at a data rate of 40 Gb/s and higher for forward error correction.     

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTs

A 50-Gb/s 4:1 multiplexer (MUX) and 1:4 demultiplexer (DEMUX) chip set using InP high electron mobility transistors (HEMTs) is described. In order to achieve wide-range bit-rate operation from several to 50 Gb/s, timing design inside the ICs was precisely executed. The packaged MUX operated from 4 to 50Gb/s with >1-V/sub pp/ output amplitude, and the DEMUX exhibited >180/spl deg/ phase margin from 4 to 50 Gb/s for 2/sup 31/-1 pseudorandom bit sequence (PRBS). Furthermore, 50-Gb/s back-to-back error-free operation for 2/sup 31/-1 PRBS was confirmed with the packaged MUX and DEMUX.