Efficient macromodeling of defect propagation/growth mechanisms inVLSI fabrication

Particulate contamination deposited on silicon wafers is typically the dominant reason for yield loss in VLSI manufacturing. The transformation of contaminating particles into defects and then electrical faults is a very complex process which depends on the defect location, size, material, and the underlying IC topography. An efficient defect macromodeling methodology based on the rigorous two-dimensional (2-D) topography simulator METROPOLE, has been developed to allow the prediction and correlation of the critical physical parameters (material, size, and location) of contamination in the manufacturing process to device defects. The results for a large number of defect samples simulated using the above approach were compared with the data gathered from the AMD-Sunnyvale fabline. A good match was obtained indicating the accuracy for our method of developing contamination to defect propagation/growth macromodels     

Formation of MOS Gates by rapid thermal/microwave remote-plasma multiprocessing

A novel cold-wall single-wafer lamp-heated rapid thermal/ microwave remote-plasma multiprocessing (RTMRPM) reactor has been developed for multilayer in-situ growth and deposition of dielectrics, silicon, and metals. This equipment is the result of an attempt to enhance semiconductor processing equipment versatility, to improve process reproducibility and uniformity, to increase growth and deposition rates at reduced processing temperatures, and to achieve in-situ processing. For high-performance MOS VLSI applications, a variety of selective and nonselective tungsten deposition processes were investigated in this work. The tungsten-gate MOS devices fabricated using the remote-plasma multiprocessing techniques exhibited negligible plasma damage and near-ideal electrical characteristics. The flexibility of the reactor allows independent optimization of each process step yet permits multiprocessing.     

火炮声探测装备辅助训练系统

针对火炮声探测系统在日常训练中受声源限制等问题,研制了火炮声探测装备辅助训练系统。该系统由数据交换机模拟设备和目标模拟机组成（平板电脑）,监控软件加装在数据综合处理终端设备,用来监控数据综合处理终端的功能和操作,数据交换机模拟设备用于模拟实装数据交换机设备的功能和操作,目标模拟机用于构建声测作业的虚拟战场环境,为数据综合处理终端设备提供虚拟的炮位或者炸点信号,用于完成火炮声探测系统信号处理设备的模拟操作训练。     

Integrated-circuit reliability simulation with emphasis on hot-carrier effects

Reliability assurance and enhancement of analog VLSI circuits are of fundamental importance in the design of high quality signal processing and computing systems. An analog integrated circuit may fial due to degradation of some critical transistors. In this paper, strategies for use in a hierarchical reliability simulation environment covering various levels of VLSI circuit design are presented. Hot-carrier effects are used to demonstrate the prediction of degradation in circuit performance. This degradation information is propagated through the design hierarchy, with the data at each stage conforming with the complexity of representation at that stage. Circuit topology changes may be made at different levels to reduce the intensive electrical stress applied to weak components. At the top level the chip degradation information is essential for the design of reliable VLSI systems. The method used to include the first-order ac degradation effects into the circuit reliability simulator is described. Experimental results on inverters, precharging circuitry for sense amplifiers, and operational amplifiers designed in submicron technologies are presented.This research was partially supported by National Science Foundation under grant MIP-8710825 and by industrial grants from Samsung Electronics Co. and TRW Inc.     

GSM网络隐性故障排查探讨

对于GSM网络中的设备故障,有些会触发相关故障告警,可称为显性故障。另外,有部分设备故障会影响网络正常运行,但却不会直接触发告警,这类故障称之为隐性故障,主要包括TRX、CDU、天线、背板、总线和各种连线设备,在软件、内部处理模块和连接方面等出现的问题。针对GSM网络隐性故障,首先要判断区分故障的类型,再根据实际工作经验将坏件替换或通知维护人员进行调测解决隐性故障。     

A 32-Bit Custom VLSI Processor for Communications Network Nodes

Aimed at the application to processors used in communications networks, three kinds of custom CMOS VLSI chips, each integrating approximately 10 kilogates, were developed. During the development of these chips, we overcame various restrictions on the VLSI design, such as input/output pin limitations, bug correction difficulty, and input/output signal delay. A combination of the software and hardware simulators efficiently eliminated logic errors. Microprogram control memory is placed externally to VLSI chips to facilitate tentative correction of possible remaining errors. Two types of processors sharing uniform architecture were also developed for an overall optimum cost-effectiveness using these VLSI chips. One uses all three kinds of VLSI chips and is suitable for switching and communications processing applications. The other includes one VLSI chip and consists of a single printed circuit board. It is suitable for a portable console processor or a processor imbedded in various equipment. These VLSI processors are being introduced in large numbers in communications networks in Japan.     

VLSI for high-performance graphic control utilizing multiprocessor architecture

This paper describes the VLSI for high-performance graphic control which utilizes two-level multiprocessor architecture. The VLSI chip is constructed of multiprocessor modules processing in parallel, and each processor module is constructed of multiexecutors using pipeline processing. This dedicated VLSI chip, designated as advanced CRT controller (ACRTC), has three processor modules, each independently controlling drawing, display, and timing. The graphic architecture of the drawing processor, which controls graphic drawing, is described. A high-level graphic language based on anX-Ycoordinate system is adopted. High-speed drawing is realized (drawing rate is 500 ns/pixel for drawing a line) by pipeline processing with three executors, the logical address executor, physical address executor, and color data executor.     

Electro-thermal and logi-thermal simulation of VLSI designs

Due to severe thermal problems of today's VLSI integrated circuits the need for reliable and quick thermal, electro-thermal and logi-thermal simulation tools is increasing, In this paper, we discuss the latest advances in the SISSI package (simulator for integrated structures by simultaneous iteration) which is a tool developed originally for analog VLSI design. The improvements include electro-thermal ac and transient simulation and the consideration of the thermal voltage of Si-Al contacts. Furthermore, we introduce a new module of SISSI, LOGITHERM, which is aimed at the self-consistent logic and thermal simulation of large digital VLSI designs. The features of our simulator package are highlighted by simulation examples that are compared in most cases with measurement results     

Reconfigurable architectures for VLSI processing arrays

The paper presents the problem of fault tolerance in VLSI array structures: its aim is to discuss architectures capable of surviving a number of random faults while keeping costs (in terms of added silicon area and of increased processing time) as low as possible. Two different approaches are presented, both based upon introduction of simple patterns of faults and by global reconfiguration techniques (rather than one-to-one substitution of faulty elements by spare ones). Various solutions are compared, and relative performances are discussed in order to determine criteria for selecting the one most suitable to particular applications.     

Quick-turnaround-time improvement for product development andtransfer to mass production

We describe equipment and facility operational methods in a production fab which are designed to achieve quick-turnaround-time (QTAT) manufacturing and ease product transfer from development to mass production. An advanced CIM system with precise lot management is introduced to keep the optimum balance of manufacturing TAT and throughput. Substantial end-user computing reduces the engineering holding time for handling development lots. In situ monitoring technologies are applied for the utilization enhancement of plasma-assisted equipment. A 9% manufacturing TAT reduction and a 14% throughput increase are estimated using a manufacturing simulator. The number of wafers in QTAT lots is reduced for processing time reduction. As a result, manufacturing TAT of QTAT lots with reduction from 24 wafers to three is reduced to 56% compared with that of normal lots in the production fab. This new production fab realizes QTAT development and agile product transfer from development to mass production with full process compatibility     

Fault Emulation for Dependability Evaluation of VLSI Systems

Advances in semiconductor technologies are greatly increasing the likelihood of fault occurrence in deep-submicrometer manufactured VLSI systems. The dependability assessment of VLSI critical systems is a hot topic that requires further research. Field-programmable gate arrays (FPGAs) have been recently pro posed as a means for speeding-up the fault injection process in VLSI systems models (fault emulation) and for reducing the cost of fixing any error due to their applicability in the first steps of the development cycle. However, only a reduced set of fault models, mainly stuck-at and bit-flip, have been considered in fault emulation approaches. This paper describes the procedures to inject a wide set of faults representative of deep-submicrometer technology, like stuck-at, bit-flip, pulse, indetermination, stuck-open, delay, short, open-line, and bridging, using the best suitable FPGA- based technique. This paper also sets some basic guidelines for comparing VLSI systems in terms of their availability and safety, which is mandatory in mission and safety critical application contexts. This represents a step forward in the dependability benchmarking of VLSI systems and towards the definition of a framework for their evaluation and comparison in terms of performance, power consumption, and dependability.     

Synergistic use of soft computing technologies for fault detection in gas turbine engines

In this paper, we present a synergistic approach to startup fault detection and diagnosis (FDD) in gas turbine engines. The method employs statistics, signal processing, and soft computing techniques in a complementary manner to address fault detection at transient conditions. Traditional turbine engine FDD methods are based on engine data collected at steady-state conditions. However, incipient faults are difficult to diagnose using steady-state engine data; only engine faults that are fairly developed can be detected using conventional methods. Because incipient engine component faults are often manifest in the engine startup characteristics, we present a method to characterize the engine transient startup. Engine sensor data during engine startup are recorded in time series format. The sensor profiles corresponding to "good" and "bad" engine startups are sampled using the bootstrap technique. A feature vector is extracted in two steps, and signal processing is followed by the feature vector selection. In the signal processing step, principal component analysis (PCA) is applied to reduce the samples consisting of sensor profiles into a smaller set. In the feature vector selection step, a cost function is defined, and important discriminating features for fault diagnosis are distilled from the PCA output vector. The features obtained from this step are then classified using neural-network-based methods. The "leave-one-out" approach to cross validation is applied to obtain an objective evaluation of the neural network training. The proposed FDD method is evaluated using actual engine startup data, and the results are presented.     

兆位电路用高纯水,气和化学试剂的质量控制

本文阐述了高纯水、高纯气和高纯化学试剂的质量对兆位电路的影响,研究了高纯水中颗粒、金属、非金属、细菌以及总有机炭对VLSI性能的影响,研究了半导体器件工艺中氯化氢、氨、氮及硅烷气体中氧、水、二氧化碳、总碳氢化物等杂质对VLSI工艺的影响;研究了化学试剂中杂质对VLSI工艺的影响。     

Highly regular, modular, and cascadable design of cellularautomata-based pattern classifier

This paper enumerates a new approach to the solution of classification problems based on the properties of Additive Cellular Automata. Classification problem plays a major role in various fields of computer science, such as grouping of the records in database systems, detection of faults in VLSI circuits, image processing, and so on. The state-transition graph of Non-group Cellular Automata (CA) consists of a set of disjoint trees rooted at some cyclic states of unit cycle length - thus forming a natural classifier. First a scheme of classifying the patterns distributed into only two classes has been dealt with. This has been further extended for solution of the multiclass classification problem. The Multiclass Classifier saves on an average 34% of memory as compared to the straight-forward approach storing directly the class of each pattern. A regular, modular, and cascadable hardware implementation of the classifier has been presented which is highly suitable for VLSI realization. The design has been specified in Verilog and verified for functional correctness     

A hardware accelerator for two-dimensional image analysis

This paper describes the architecture and operation of a new hardware accelerator called MultiRing for performing various geometrical operations on two-dimensional image space. This hardware architecture is shown to be applicable for design rule checking in VLSI layout and many image processing operations including noise suppression and contour extraction. It has both a fast execution speed and extremely high flexibility. Each row data stored in ring memory is processed in the corresponding processor in full parallelism. Each processor is simultaneously configured by the instruction decoder/controller to perform one of the 20 basic instructions each ring cycle, which gives MultiRing maximal flexibility in terms of design rule change or the instruction set enhancement. Correct functional behavior of MultiRing was confirmed by successfully running a software simulator having one-to-one structural correspondence to the MultiRing hardware.     

Quietest: A methodology for selecting I DDQ test vectors

Even high stuck-at fault coverage manufacturing test programs cannot assure high quality for CMOS VLSI circuits. Measurement of quiescent power supply current (I _DDQ ) is a means of improving quality and reliability by detecting many defects that do not have appropriate representation in the stuck-at fault model. Since each I _DDQ measurement takes significant time, a hierarchical fault analysis methodology is proposed for selecting a small subset of production test vectors for I _DDQ measurements. A software system QUIETEST has been developed on the basis of this methodology. For two VLSI circuits QUIETEST selected less than 1% of production test vectors for covering all modeled faults that would have been covered by I _DDQ measurement for all of the vectors. The fault models include leakage faults and weak faults for representing defects such as gate oxide shorts and certain opens.     

电子设备故障诊断技术综述

随着电子技术的发展,电子设备组成的复杂化和智能化不断提高.IC芯片制造工艺的不断提高使得VLSI电路的集成密度增加,亦加大了电子设备故障测试的复杂性和难度.结合当前电子设备故障诊断的最新成果与发展动态,综述了故障诊断与检测的三种主流方法:基于解析模型的方法、基于信号处理的方法和基于知识的方法.总结了目前电子设备故障诊断技术的发展概况和趋势.     

Quantum Computer Simulator Based on the Circuit Model of Quantum Computation

A quantum computer simulator is presented. This simulator is an engineering work and no deep understanding of quantum mechanics is required from the user. The simulator is based on the circuit model of quantum computation in which quantum gates act on quantum registers which comprise a number of quantum bits (qubits). The inputs to the simulator are the initial states of the qubits that form a quantum register and the quantum gates applied at each computation step. The inputs are entered through a graphical user interface. The outputs of the simulator are the matrices that represent the quantum register state at each quantum computation step and graphical outputs that show the probability of measuring each one of the possible quantum register base states and the phase of each state at each computation step. The well-known Deutsch's algorithm and the quantum Fourier transform, which is the base of many quantum algorithms, are presented using this simulator. Furthermore, the generation and variation of entanglement during quantum computations can be calculated using this simulator. The quantum computer simulator is a useful tool for the study of quantum computer circuits, quantum computing, and the development of new quantum algorithms.     

Hot-carrier generation in submicrometer VLSI environment

Submicrometer MOSFETs may suffer from reliability degradation, which has a strong correlation with substrate current. In order to know what is happening to substrate current in a VLSI environment, a substrate-current circuit simulator is developed. The simulator is applied to MOS unit circuit blocks, VLSI static memories, and dynamic memories, and their hot-carrier duty ratios are calculated. A new circuit technology, called normally-on enhancement MOSFET insertion (NOEMI), is proposed which can suppress hot-carrier generation. Several design implications for submicrometer VLSIs are obtained through the analysis.