Formation of Two-Component Vertical Contact Structures for Mounting Integrated-Circuit Chips

The technological capabilities of the layer-by-layer electrochemical formation of vertical contact structures based on a copper–tin system for mounting silicon chips, including 3D technologies, have been considered. The possibility of fixing a chip–board clearance for the preventing a short circuit between the contact areas with the solder material has been shown.     

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips

This paper deals with the design of SOC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail Architecture, as this architecture, unlike others, allows not only for efficient core-internal testing, but also for efficient testing of the circuitry external to the cores. We present a novel heuristic algorithm that effectively optimizes the TestRail Architecture for a given SOC by efficiently determining the number of TestRails and their widths, the assignment of cores to the TestRails, and the wrapper design per core. Experimental results for four benchmark SOCs show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.     

给通信产品装上"中国芯"

信息产业是近百年来发展最快的产业，信息产业的快速发展使人类的生活发生了重大改变。在中国，随着电子信息产品制造业成为制造业的第一大产业，其在国民经济中的重要地位日益凸现，而电子信息产品制造业的发展，又使电子产品的“粮食”———集成电路(IC)芯片的需求量越来越大。对此，国务院在2000年颁布了18号文件———《鼓励软件产业和集成电路产业发展的若干政策》，以鼓励和扶持发展集成电路产业。1 集成电路的应用对信息产业的影响由于信息产业的迅猛发展，中国已成为集成电路的消耗大国，2001年中国集成电路的需求量达全球总需求…     

迎新年推新品--研祥智能发布新品策略

日前,国内最大的全系列工业PC产业集团深圳市研祥智能科技股份有限公州(以下简称研祥智能股份)发布了其2002年的全系列工业PC产品体系和产品策略。此次发布的产品体系中     

功率晶体管热阻测试条件确定方法

以B2-01C(TO-3)型金属封装的3DK109E型功率开关晶体管为实验对象,研究了双极型功率晶体管热阻测试条件的确定方法.以图解的形式着重介绍了测试电流(IM)及基极-发射极电压温度系数(M)、加热脉冲持续时间(tp)、加热功率条件(VCB、IE)、测量延迟时间(td)等热阻测试条件的确定过程.     

新型的EPON结构及其保护倒换策略

本文提出一种新型的EPON结构,可以实现ONU间直接对等通信。ONU之间的通信不再需要OLT的转发,提高了系统带宽利用率,降低包传输时延。同时提出了该网络结构下的保护倒换方案,实现快速故障检测和倒换.保证网络的高可靠性。     

汽车电子芯片EMC测试标准研究

在汽车电子产品所采用的电磁兼容测试标准的基础上,以功率驱动芯片为例,提出了汽车电子芯片级电磁兼容测试的必要性,并重点介绍了集成电路电磁发射测试标准IEC61967和集成电路电磁抗扰度测试标准IEC62132。     

A Comparison of Test and Model-Predicted RF-Pulse Susceptibilities of UHF Transistors

A semiconductor thermal-damage model was presented previously. Accuracy verification was limited to dc pulses and a damped sinusoidal waveform. Data published on UHF transistors allow additional model verification to RF pulses. 1 Results confirm that dc-pulse data are sufficient to predict RF-pulse damage levels.     

纵向NPN管ESD保护结构的设计与分析

针对一种5V0.6μm BiCMOS工艺的纵向NPN管,设计了ESD保护结构。为了克服传统纵向NPN管ESD自触发结构触发电压较高的缺陷,提出一种带P+/N阱二极管的改进型自触发ESD结构,利用NPN管集电极与基极之间的寄生电容和二极管作为电容耦合元件。流片及测试结果表明,该保护结构的触发电压得到有效降低,且抗ESD能力超过4kV的人体模型。     

FinFET纳电子学与量子芯片的新进展

综述了后摩尔时代中两大发展热点:鳍式场效应晶体管(FinFET)纳电子学和基于量子计算新算法的量子芯片的发展历程和近两年的最新进展。在FinFET纳电子学领域,综述并分析了当今Si基互补金属氧化物半导体(CMOS)集成电路的发展现状,包括FinFET的发展、10 nm和7 nm技术节点的量产、5 nm和3 nm技术节点的环栅场效应晶体管(GAAFET)和2 nm技术节点的负电容场效应晶体管(FET)的前瞻性技术研究以及非Si器件(InGaAs FinFET、WS2和MoS2两种2D材料的FET)的探索性研究。指出继续摩尔定律的发展将以Si基FinFET和GAAFET的技术发展为主。在量子芯片领域,综述并分析了超导、电子自旋、光子、金刚石中的氮空位中心和离子阱等五种量子比特芯片的发展历程,提高相干时间、固态化及多量子比特扩展等的技术突破,以及近几年在量子信息应用的新进展。基于Si基的纳米制造技术和新的量子计算算法的结合正加速量子计算向工程化的进展。     

畅谈新一代LTE网络优化测试产品——LTE空中接口监测仪

LTE空中接口监测仪表不仅仅是传统仪表的延伸与拓展,作为一种新型测试仪表,它将在LTE网络规划、建设、优化中发挥出重大的作用。本文首先通过介绍移动通信新技术、新网络、新业务的发展,引出了LTE空中接口监测仪产生的背景及必要性。随后着重介绍了产品架构、关键技术及主要功能,最后结合网络建设的不同阶段,对产品的应用场景进行了分析。     

A New Analog Buffer Using Low-Temperature Polysilicon Thin-Film Transistors for Active-Matrix Displays

In this paper, a new source-follower-type analog buffer for active-matrix displays, designed by using low-temperature polysilicon thin-film transistors (TFTs), is proposed. The buffer, consisting of five n-type polysilicon TFTs, one bias voltage, and an additional control signal, exhibits high immunity to threshold voltage and mobility variations. The functionality of the proposed buffer was verified by HSPICE simulations. In order to obtain realistic simulations, the TFT model parameters used for the simulations were extracted from fabricated TFTs using the Silvaco tools (ATLAS). The proposed buffer has 7-bit output voltage with the dynamic output voltage range of 7.5 V ranging from 2.5 to 10 V and with resolution up to 0.03 V     

多媒体音像压缩芯片的新进展

本文简要综述用于多媒体视频、音频压缩的ＭＰＥＧ－１编／解码芯片新进展。     

一种提高硅双极器件频率和功率的新技术

提出了一种能同时提高硅双极器件频率和功率的新技术－具有深阱终端结构的新型梳状深阱结构技术。采用ＭＥＤＩＣＩ模拟分析表明,该技术可交双极器件的击穿电压ＢＶＣＢ０提高到平行平面结的９０％以上;可减小寄生效应和漏电流,有助于提高小电流β０;可适当的增加集电区掺杂浓度,减小τｄ,同时提高ＩＣＭ和Ｐｏ。     

打造信息安全高端芯片向用户提供自主创新产品

在经过了多年的专业集成电路设计与开发的经验积累之后,北京宏思电子技术有限责任公司将目光锁定在安全芯片的开发与应用推广领域。在成功推出WNG数字物理噪声源系列芯片和SSX30国家标准分组密码算法系列芯片之后,北京宏思公司又于去年研发成功了面向PKI体系的SSX14系列信息安全系统级(SOC)集成电路,     

内容中心网络中面向隐私保护的协作缓存策略

针对内容中心网络节点普遍缓存带来的隐私泄露问题,在兼顾内容分发性能的基础上,该文提出一种面向隐私保护的协作缓存策略。该策略从信息熵的角度提出隐私度量指标,以增大攻击者的不确定度为目标,首先对于缓存策略的合理性给予证明;其次,通过构建空间匿名区域,扩大用户匿名集合,增大缓存内容的归属不确定性。缓存决策时,针对垂直请求路径和水平匿名区域,分别提出沿途热点缓存和局域hash协同的存储策略,减小缓存冗余和隐私信息泄露。仿真结果表明,该策略可减小内容请求时延,提高缓存命中率,在提升内容分发效率的同时增强了用户隐私保护水平。     

A Ring Architecture Strategy for BIST Test Pattern Generation

This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under test (CUT), i.e., no test point insertion. The set of patterns generated by a pseudo-random pattern generator, e.g. a Linear Feedback Shift Register (LFSR), is transformed into a new set of patterns that provides the desired fault coverage. To transform these patterns, a ring architecture composed by a set of masks is used. During on-chip test pattern generation, each mask is successively selected to map the original pattern sequence into a new test sequence. We describe an efficient algorithm that constructs a ring of masks from the test cubes provided by an automatic test pattern generator (ATPG) tool. Moreover, we show that rings of masks are implemented very easily at low silicon area cost, without requiring any logic synthesis tool; a combinational mapping logic corresponding to the masks is placed between the LFSR and the CUT, together with a looped shift register that acts as a mask selecting circuit. Experimental results are given at the end of the paper, demonstrating the effectiveness of the proposed approach in terms of area overhead, fault coverage and test sequence length. Note that this paper is an extended version of [1].     

MoDiVHA: A Hierarchical Strategy for Distributed Test Assignment

Distributed diagnosis allows a set of fault-free nodes to monitor the state of all nodes of a given system. Diagnosis is based on the results of tests, which are assigned among system nodes. Hierarchical testing assignments lead to efficient and scalable diagnosis algorithms, both in terms of the number of tests executed, and the latency. In this work we present a novel hierarchical testing strategy, called MoDiVHA. By obtaining as much diagnostic information as possible from each test, and avoiding tests on nodes about which information has been already obtained, MoDiVHA executes less tests in comparison with previously proposed assignments. Experimental results are presented from three series of simulations conducted to compute the number of tests and diagnosis latency for various system sizes and fault situations.