Measurement and analysis of charge injection in MOS analog switches

The analysis has been extended to the general case including signal-source resistance and capacitance. Universal plots of percentage channel charge injected are presented. Normalized variables are used to facilitate usage of the plots. The effects of gate voltage falling rate, signal-source level, substrate doping, substrate bias, switch dimensions, as well as the source and holding capacitances are included in the plots. A small-geometry switch, slow switching rate, and small source resistance can reduce the charge injection effect. On-chip test circuitry with a unity-gain operational amplifier, which reduces the disturbance imposed by measurement equipment to a minimum, is found to be an excellent monitor of the switch charge injection. The theoretical results agree with the experimental data.     

Charge injection in analog MOS switches

Charge injection in MOS analog switches, also called pass transistors or transmission gates, is approached by using the continuity equation. Experimental results show the negligible influence of substrate current which leads to a unidimensional model. An easy-to-handle simplified model is deduced and its predictions compared to the injection obtained by measurements. It is shown that this model, which can be used to implement various strategies to reduce charge injection, is valid in any realistic situation.     

A new quantitative model for weak inversion charge injection inMOSFET analog switches

This paper proposes a new model concerning the channel charges in weak inversion injected from a turn-off MOSFET into a holding capacitor. This portion of charge injection has recently been newly observed, showing a significant contribution to the switch-induced error voltage on the switched capacitor. Our model is derived at the critical point where the device is operated in the transition region between strong inversion and weak inversion. This point has been expressed explicitly as a function of the DC input voltage, the threshold voltage, and the fall time of the gate voltage. The ability of the model in accurately determining quantitatively the impact of the weak inversion charge injection on the error voltage has been extensively judged experimentally and by two-dimensional mixed-mode simulation for a wide variety of design parameters such as the channel width and length, the holding capacitance, the fall time of the gate voltage, and the DC input voltage The assumptions utilized in the model development have also been validated     

Measurement and modeling of charge feedthrough in n-channel MOS analog switches

Charge feedthrough in analog MOS switches has been measured. The dependence of the feedthrough voltage on the input and tub voltages, device dimensions, and load capacitances was characterized. Most importantly, it was observed that the feedthrough voltage decreases linearly with the input voltage. The significance of this observation when considering harmonic distortion in sample-and-hold circuits is discussed. A first-order computer simulation based on the quasi-static small-signal MOSFET capacitances shows good agreement with experimental results.     

Frequency response of charge transfer in MOS inversion layers

The dynamics of charge transfer from a reservoir into an MOS inversion layer, which limits the frequency response of an MOS transistor or a charge-coupled device, is investigated. Using Berman and Kerr's model of space-charge capacitance in the semiconductor, a small-signal distributed model is developed for an MOS structure which transfers charge in an inversion channel due to a variation in the gate voltage. The dynamics of the charge transfer is characterized by a time constant which is determined by the length of the inversion channel and its mobility. Experimental data of gate capacitance vs frequency, taken from a test structure with a diffused source/drain well, are satisfactorily fitted by theoretical curves derived from the model. The channel mobility is precisely determined from the adjusted time constant. The influence of interface states on the capacitance-frequency relationship is also briefly discussed.     

Accuracy of conventional inversion charge modeling in scaled down MOS devices

The density of surface inversion charge in MOS structures is typically calculated using the relation Q = cox(V_G − V_T). In the present article we try to quantitatively assess the goodness of this relation in the case of MOS devices scaled down according to constant field scaling and constant voltage scaling principles by comparing the inversion charge given by this relation to the inversion charge obtained by numerically solving the Poisson equation in one dimension. It turns out that while in the case of constant field scaling the conventional relation for inversion charge becomes progressively erroneous, the same is not true for devices scaled down according to constant voltage scaling.     

A comparison of MOS inversion layer charge and capacitance formulas

A test is made of a recent proposal by Lewyn and Meindl for approximation of MOS inversion layer charge and substrate capacitance. Included in the test are the charge sheet formula and a new formula derived here which includes the pinning of the depletion layer width in strong inversion. Comparison with numerical calculation shows the Lewyn-Meindl result for charge density is less accurate than the charge sheet result over the entire subthreshold region. Similar inaccuracy is expected in MOS current-voltage curves in the subthreshold region and near pinch-off. The new formula is better than the other two over the entire bias range. A comparison of dc and ac substrate capacitances shows the new result to be better than both of the other formulas. In inversion, however, the percent error in dc capacitance is large. This large percent error corresponds to a small absolute error because the dc capacitance goes to zero in strong inversion. The ac capacitance error in strong inversion is ∼5 percent because of neglect of the ac inversion layer redistribution. Percent error curves for all three formulas are presented as a function of band bending and reverse bias.     

便携设计中模拟开关的变迁

引言 与电源设计应用中传统大功率MOSFET开关和存储应用中多位数据总线开关相比，模拟开关大大不同。一般来讲，模拟开关主要用于切换手机等便携式设计中的小功率模拟信号。但是．在最近的便携式设计中附加功能的推动下，模拟开关从传统的低带宽音频开关发展成为高速混合信号开关。由于模拟开关具有低功耗、低漏电流及小封装等特点，在某些设计中甚至可以将其用作低功耗DC信号开关。     

MOS analog function synthesis

The design of a monolithic MOS parametric analog function synthesizer is described. The contour and voltage scaling of the nonlinear function to be synthesized are determined by a set of input bias voltage parameters, and are independent of temperature and processing variations. Experimental results showing synthesis precision on the order of 2% over temperature are presented. The particular application of generating a voltage that is a nonlinear function of chip temperature for compensation purposes is addressed.     

Moderate inversion in MOS devices

The region of validity of common approximations for weak and strong inversion is examined. It is shown that at the lower limit of what is often defined as strong inversion region, incremental quantities such as transconductance can be an order of magnitude smaller than the value predicted by using common strong inversion approximations. It is suggested that the limits of validity of widely used approximations for various quantities in weak and strong inversion can be judged by the value of a single parameter, namely the ratio of the inversion layer capacitance to the sum of the oxide capacitance and the depletion region capacitance. It is shown that in the region where this parameter takes values above 0.1, weak inversion approximations are in serious error; similarly, in the region where this parameter takes values below 10, strong inversion approximations are in serious error. The definition of a “moderate inversion region” between the above two limit points is proposed. The width of this region is calculated for a variety of process parameters and values of the quasi-Fermi potential difference, and is found to exceed 0.5 V in many cases. The accuracy of commonly used approximations for the extrapolated threshold voltage is examined.     

Trimming analog circuits using floating-gate analog MOS memory

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100°C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV     

Integrated MOS analog delay line

A 16-stage, fixed or variable analog delay line that makes use of integrated p-channel MOS field-effect transistors is described. The delay line relies on `sample' and `hold' techniques and makes use of the inherent characteristics of p-channel MOS transistors. The delay line provides unit gain with a dynamic range of 1 volt. The bandwidth of the delay line is 0.8 MHz under nonsampling conditions. The lowest sampling rate was found to be 50 Hz. A built-in capacitive compensation technique using signals opposite in phase reduces feedthrough of the sampling signal and final filtering requirements. Investigation of the problems of obtaining unity gain and dynamic range led to the development of a computer-aided analysis that provides a family of dc transfer characteristics of cascaded p- channel MOS `half-stages' when a variation of either a material or electrical parameter is made.     

Near-interface trapped charge induced by Fowler-Nordheim injection in hydrogen or argon annealed MOS capacitors

By applying Fowler-Nordheim stress to a metal-oxide-semiconductor capacitor, we studied the relationship between hydrogen anneal temperature and near-interface trapped positive charge. Wet oxides annealed with hydrogen at temperatures between 400 and 1000°C exhibited a maximum near-interface charge density after the 800°C anneal. A similar set of oxides annealed in Ar showed only a continual decrease with increased anneal temperature. Based on our understanding of earlier nuclear reaction analysis studies by Myers, we suggest that hydrogen in the form of O-H is associated with the increase in the near-interfacial positive charge density.     

Experimental MOS C-V data in strong inversion

Experimental capacitance-voltage (C-V) data are presented to verify recent theories of surface minority carrier redistribution in MOS capacitors biased near strong inversion. The surface layer of minority carriers shunts a portion of the surface space-charge layer resulting in a small capacitance minimum and a slightly larger asymptotic capacitance in strong inversion than predicted by older theory. The agreement between the experiment and the recent theory is very good. The experimental asymptotic capacitance in strong inversion is slightly larger than predicted. This discrepancy is attributable to the surface quantization effect not contained in the recent theory.     

Noise associated with charge injection into-a CCD by current integration through a MOS transistor

The noise charge resulting from integrating a noisy current at a CCD input (equivalent to a MOS transistor) is evaluated. The noise contributions of the signal source and of the input transistor can be separated from other components of the CCD noise. Moreover, our measurements show a very good agreement with previously reported 1/f noise results for MOS transistors working in weak or strong inversion regimes.     

MOS场效应晶体管降低串扰对模拟开关的影响

有些经济实惠的模拟复用器/去复用器集成电路,如CD4053和CD4066,经常被用作信号分配器.这些数控模拟开关都具有很低的导通电阻.但是,在所有信道都在同一封装之中的情况下,串扰可能就是令人头痛而又无法避免的问题了.     

MOS switched-capacitor analog sampled-data direct-form recursive filters

A new technique enabling the integration of audio frequency filters using standard MOS technology is described. This approach uses ratioed MOS capacitors, MOS amplifiers and switches to realize precision multiplication, summation, and delay functions. With these elements an analog sampled-data direct-form recursive filter, having the general biquadratic transfer function, was integrated in MNOS technology. This filter had a Q=19/spl plusmn/1 without external trimming and it could be electrically programmed into low-pass, bandpass, and high-pass responses. This biquadratic section can be used as a building block for higher order filters. The direct form switched-capacitor offers some useful advantages in comparison to the switched-capacitor integrator approach. These are the rejection of MOS amplifier noise and power supply noise below one-half the sampling rate, less silicon area especially when implementing high Q poles, and potential for multiplexing two or more filters.     

A sampled analog MOS LSI adaptive filter

Describes a novel realization of an adaptive filter using sampled analog MOS LSI techniques in which the basic functional block is an electrically programmable transversal filter whose tap weights are modified according to the least mean square algorithm. A rotating tap weight structure is used to realize a 32-tap programmable transversal filter with features for the adaptive operation included on an NMOS silicon gate chip. A wide range of magnitude and phase characteristics have been used to test this system and the results on the residual error and the convergence time under different conditions are reported. Some practical limitations are also presented.     

Subthreshold analysis of an MOS analog switch

Charge injection error in the presence of subthreshold effects has been analyzed. It is confirmed that the subthreshold effect is significant at low voltage falling rates. A simplified model is derived using an appropriate approximation. Predictions are compared to the results of a SPICE simulation, a nonquasi-static (NQS) model simulation and experimental results. Excellent agreement between the modified and NQS model and recently published experimental results was obtained. This analytical model is computationally efficient compared to the SPICE and NQS models and provides physical insight into the switching errors     

MOS charge pumps for low-voltage operation

New MOS charge pumps utilizing the charge transfer switches (CTSs) to direct charge flow and generate boosted output voltage are described. Using the internal boosted voltage to backward control the CTS of a previous stage yields charge pumps that are suitable for low-voltage operation. Applying dynamic control to the CTSs can eliminate the reverse charge sharing phenomenon and further improve the voltage pumping gain. The limitation imposed by the diode-configured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude. Using the new circuit techniques, a 1.2-V-to-3.5-V charge pump and a 2-V-to-16-V charge pump are demonstrated