0.18-μm fully-depleted silicon-on-insulator MOSFET's

High-performance 0.18-μm gate-length fully depleted silicon-on-insulator (FD-SOI) MOSFET's were fabricated using 4-nm gate oxide, 35-nm thick channel, and 80-nm or 150-nm buried oxide layer. An elevated source/drain structure was used to provide extra silicon during silicide formation, resulting in low source/drain series resistance. Nominal device drive currents of 560 μA/μm and 340 μA/μm were achieved for n-channel and p-channel devices, respectively, at a supply voltage of 1.8 V. Improved short-channel performance and reduced self-heating were observed for devices with thinner buried oxide layers     

Measurement and modeling of circuit speed of CMOS on oxygen-implanted SOI

The dependence of the stage delay of CMOS ring oscillators on the voltage applied to the underlying silicon substrate has been investigated for SOI substrates formed by high-dose oxygen ion implantation. Improvements in speed of up to 30 percent are produced when the silicon under the isolating oxide is depleted. This situation occurs naturally for zero applied voltage when the substrate is lightly doped p-type and gives the oxygen-implanted SOI similar speed performance to other forms of SOI with thicker isolation layers. The increased speed is in good agreement with predictions made using SPICE simulation and modeled circuit capacitances.     

Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.     

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65 nm FD-SOI/SON CMOS technology

The paper presents a detailed study on the sub-1 V high speed operation with reduced leakage design techniques for conventional 6T Static Random Access Memory (SRAM) on fully depleted Silicon-on Insulator (FD-SOI) and fully depleted Silicon-on-Nothing (FD-SON) technology. Performance of SON MOSFET is found to be significantly better both in terms of power and speed from its equivalent SOI device. Future devices with advanced technology are promising for low-power application. The most promising high-speed, low-power operation techniques are introduced, analyzed and compared into 65 nm low-power FD-SOI/SON technology. Hspice simulations conclude Drive Source Line (DSL) architecture as the best option for high speed operation in sub 100 nm technology without affecting the Static Noise Margin (SNM) of the cells.     

Comparison of hole mobility in LOCOS-isolated thin-film SOIp-channel MOSFET's fabricated on various SOI substrates

The hole mobility of LOCOS-isolated thin-film silicon-on-insulator (SOI) p-channel MOSFET's fabricated on SOI substrates with different buried oxide thickness has been investigated. Two types of SOI wafers are used as a substrate: (1) SIMOX wafer with 100-nm buried oxide and (2) bonded SOI wafer with 100-nm buried oxide. Thin-film SOI p-MOSFET's fabricated on SIMOX wafer have hole mobility that is about 10% higher than that on bonded SOI wafer. This is caused by the difference in the stress under which the silicon film is after gate oxidation process. This increased hole mobility leads to the improved propagation delay time by about 10%     

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFET's, the proposed SOI MOSFET's have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFET's have a fully bulk CMOS compatible layout and process     

Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices     

Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness most be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices     

An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature

This letter provides an assessment of single-electron effects in ultrashort multiple-gate silicon-on-insulator (SOI) MOSFETs with 1.6-nm gate oxide. Coulomb blockade oscillations have been observed at room temperature for gate bias as low as 0.2 V. The charging energy, which is about 17 meV for devices with 30-nm gate length, may be modulated by the gate geometry. The multiple-gate SOI MOSFET, with its main advantage in the suppression of short-channel effects for CMOS scaling, presents a very promising scheme to build room-temperature single-electron transistors with standard silicon nanoelectronics process.     

Generation-recombination noise in the near fully depleted SIMOX SOI n-MOSFET - physical characteristics and modeling

Noise measurement in the linear regime of the device characteristics shows the evolution of an important Lorentzian-like component in the thin-film SIMOX silicon-on-insulator (SOI) n-MOSFET, during the transition from fully depleted to near fully (or partially) depleted operation. The same noise component co-exists with another Lorentzian-like component commonly observed in the kink region, thus distinguishing it from the latter, which is associated with a shot-noise mechanism. Evidence unambiguously shows that local potential fluctuations, caused by random generation-recombination (G-R) processes at bulk defects in the depleted SOI film, are primarily responsible. Extracted trap energy of /spl sim/0.4-0.45 eV below the silicon conduction band edge confirms the involvement of deep-level electron traps, which are probably linked to the residual oxygen and SiO/sub 2/ precipitates in the SOI film. A new analytical G-R noise model yields bulk traps with an average density of /spl sim/10/sup 16/ cm/sup -3/, situated at /spl sim/22-32 nm from the front interface. With an area density comparable to that of the front interface states, the proximity of these bulk traps to the conducting channel in thin-film SIMOX SOI devices accounts for the dominance of bulk-trap induced G-R noise over conventional 1/f noise due to near-interface oxide traps.     

Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts

The switching dynamics of silicon-on-insulator (SOI) high power vertical double diffused MOS (VDMOS) transistors with an inductive load has been investigated by device simulation. Unlike other conventional VDMOS devices, this device has drain contacts at the top surface. In general the switching behaviour of a power device during the unclamped inductive switching (UIS) test will determine the reliability of the power device as the energy stored in the inductor during the on state is dumped directly into the device when it is turned off. In this paper we compare the switching dynamics of the SOI VDMOS transistor with standard bulk silicon VDMOS device by doing numerical simulations. It is shown here, using 2D-device simulations that the power dissipated in the SOI VDMOS device during the UIS test is smaller by approximately a factor of 2 than in the standard bulk silicon VDMOSFET. The lower dissipation is due to the presence of the silicon film/buried oxide/substrate structure (this structure forms a SOI capacitor). In the case of the SOI VDMOS transistor the energy released from the inductor during the UIS test is stored to some extent in the SOI capacitor and partly dumped directly into the device. As a result the maximum current through the SOI device is separated in time from the maximum voltage across the device, unlike in the bulk case, thereby reducing the maximum power.     

High performance fully-depleted tri-gate CMOS transistors

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.     

Multiple layers of silicon-on-insulator islands fabrication byselective epitaxial growth

This paper presents for the first time, multiple layers of silicon-on-insulator (MLSOI) device islands fabricated using selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) techniques. MLSOI has the potential for ultra dense device integration. SOI device islands as small as 150 nm×150 nm, with thickness down to 40 nm have been fabricated. SOI device islands (5 μm×500 μm) in the second layer have shown no stacking faults in the 1290 islands inspected. To demonstrate the device quality material, fully depleted SOI (FD-SOI) P-MOSFET's were fabricated in the first layer SOI islands with gate lengths down to less than 170 nm. Typically they had low subthreshold leakage, below 0.2 pA/μm, and a subthreshold swing of 76 mV/dec was measured     

Electro-Thermally Coupled Power Optimization for Future Transistors and Its Applications

We report a novel electro-thermally coupled power-optimization methodology for future transistors. The methodology self-consistently yields the globally optimized total power and the corresponding temperature as a function of delay for a given set of transistors (bulk, double-gate FET, fully depleted SOI, and partially depleted SOI) at future technology nodes. When SPICE models are not necessarily available and simple device models are highly inadequate because of complex 2D device effects, these derived power/temperature versus delay curves serve as a comprehensive standard to compare any two transistors for future technology-node device selections. Because the power optimization is global (over various transistor parameters and includes leakage as well as dynamic power) and is self-consistently coupled to electro-thermal models, the methodology provides the optimum operational supply voltage (V_dd) and the device parameters (body thickness, equivalent oxide thickness, and gate metal work function) for future transistors targeting 45-nm technology node. Furthermore, it can be used to provide insight into advance nodes, device-specific hot-spot problems, multiple V_t, V_dd design for different functional blocks, transistor design, and evaluating the efficacy of novel thermal solutions such as superior thermal conductivity and subambient cooling.     

Fabrication of self-aligned 90-nm fully depleted SOI CMOS SLOTFETs

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured     

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOItechnology

A 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology, CMOS8S, and techniques to maintain performance are described. CMOS7S SOI, a 1.8-V/0.22-μm partially depleted SOI technology, achieves a 28% speed increase over bulk CMOS7S, and CMOS8S SOI delivers an additional 21%. In a 660-MHz CMOS8S SOI processor, the adder compensates for floating body effects in SOI devices which cause history effects, bipolar currents, and lower noise margins on dynamic circuits     

Performance advantages of 3-D digital integrated circuits in a mixed SOI and bulk CMOS design space

Three-dimensional (3-D) integrated circuits (ICs), with multiple stacked device layers, offer a unique design opportunity to use both bulk and partially depleted (PD) silicon-on-insulator (SOI) CMOS devices in a single circuit design. Such 3-D designs can, for example, minimize the body effect common in bulk designs and reduce adverse floating-body effects (FBE) common in PD SOI designs. Sequential 3-D technology such as exfoliation-based single-crystal silicon layer transfer allows a low-temperature approach to 3-D integration with high-density interconnectivity. Using the characteristics of this technology, we present the mixed SOI bulk (MSB) design approach that effectively re-maps conventional VLSI designs to the 3-D design space. Tradeoffs in delay, noise margin, power, and circuit footprint are analyzed and demonstrated through analyzes of static, dynamic, pass-transistor, and SRAM circuits.     

High-performance thin-film silicon-on-insulator CMOS transistors inporous anodized silicon

Ultrathin-film silicon-on-insulator (SOI) CMOS transistors, produced in silicon islands 100 nm thick, formed by oxidation of porous anodized silicon, are described. Both n-channel and p-channel mobilities are similar to equivalent bulk values. Subthreshold slopes are less than 80 mV/decade and junction leakages are approximately 0.1 pA/μm. No kink is seen in the output characteristics of the n-channel transistors as the silicon film is fully depleted. A ring-oscillator gate delay of 161 ps has been achieved, at a power dissipation of 270 μW/stage, for 1.5-μm gate length     

Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET'swithout self-heating

A new method for measuring the output (I_D-V_D) characteristics of SOI MOSFET's without self-heating is described. The method uses short pulses with a low repetition rate, and a reverse transient loadline construction. The technique is demonstrated by measuring 0.25 μm bulk and SOI MOSFET's with 5-nm gate oxide. Application of the method to the extraction of device temperature as a function of DC power is also illustrated     

Linearity and low-noise performance of SOI MOSFETs for RFapplications

The MOSFET parameters important for RF application at GHz frequencies: a) transition frequency, b) noise figure, and c) linearity are analyzed and correlated with substrate type. This work demonstrates that, without process changes, high-resistivity silicon-on-insulator (high-ρ SOI) substrates can successfully enhance the RF performance of on-chip inductors and fully depleted (FD)-SOI devices in terms of reducing substrate losses and parasitics. The linearity limitations of the SOI low-breakdown voltage and "kink" effect are addressed by judicious device and circuit design. Criteria for device optimization are derived. A NF = 1.7 dB at 2.5 GHz for a 0.25 μm FD-SOI low-noise amplifier (LNA) on high-ρ SOI substrate obtained the lowest noise figure for applications in the L and S-bands