Systematic design of wideband ΔΣ modulators for WiFi/WiMAX receivers

Modern multi-standard receivers in deep-submicron technologies pose significant design challenges on the analog baseband. Moving this analog filtering to the digital domain simplifies the design, yielding a process-scalable implementation. However, analog-to-digital converter (ADC) specifications now become more stringent and must be obtained by comprehending the standard and the system. Assuming a receiver NF of 5.96 dB and SNR degradation of 0.36 dB by the ADC, the proposed dual-mode WiFi/WiMAX receiver attains an input sensitivity of −74 dBm (20 MHz channel bandwidth). To accommodate the high dynamic range and the anti-alias rejection needed for the system, a Delta-Sigma (ΔΣ) ADC is proposed. Single-loop and Multi-Stage Noise-Shaping (MASH) architectures that achieve a SNR of 69 dB at a low oversampling ratio (OSR) of 8 for a conversion bandwidth of 40 MHz (108 Mbps, OFDM) are investigated at system level. Based on thermal noise, harmonic distortion, and power tradeoffs, a ΔΣ ADC design that meets the design specifications is presented.     

Compact low-power implementation for continuous-time ΣΔ modulators

This paper presents a low-area continuous time (CT) sigma–delta (ΣΔ) modulator implementation based on a local feedback. The proposed structure provides a very low impedance node without the need of classical op-amps, which leads to a reduction in power and area consumption. Two versions of a conventional first-order CT ΣΔ modulator prototype have been fabricated with the purpose of evaluating the idea. The modulator requirements have been set for a passive RFID tag with sensing capability application, so that achieving minimum active area and very low power consumption are the main objectives for the presented design. Experimental results of the first version of the modulator show 8 bits of Effective-Number-Of-Bits (ENOB) in a 25 kHz signal bandwidth with 7 μW of power consumption. The proposed implementation has also shown to be very robust against supply voltage and bias current variations. A second approach has also been designed, using the same principle of operation, in order to increase the input voltage range without any power consumption penalty at the expense of decreasing the input impedance and stingily increased area. This second approach shows 9 bits of ENOB in the same signal bandwidth with a power consumption of 4.35 μW. A Figure Of Merit (FOM) of 0.267 pJ/state has been achieved with a total area consumption (without pads) of 110 μm×125 μm in a 0.35 μm CMOS technology.     

A low-power parametric integrator for wideband switched-capacitor ΣΔ modulators

This paper proposes a new low-power MOS parametric integrator (MPI) for the design of wideband discrete time sigma-delta (ΣΔ) modulators. The MPI is implemented with MOS capacitors, which provide the required gain by switching from inversion in the sampling phase into depletion in the amplification phase. Analysis along with simulation results illustrate that MPI consumes very low power dissipation compared to the conventional active integrators with some negligible performance changes. To verify this, the MPI is used in two wideband ΣΔ modulators, one with 8-bit resolution and the other with 13-bit resolution with input bandwidth and sampling frequency of 12.5 and 200 MHz, respectively. The first one is a second order single stage ΣΔ modulator and the second one is a MASH 2-2 modulator, both implemented in 0.18-μm CMOS technology. Simulation results indicate that these modulators save a significant amount of power consumption when their second integrator is replaced by MPI.     

On the design of feed-forward ΣΔ interface for MEMS based accelerometers

High order ???? interface is popular for high resolution micro-electro-mechanical systems. Previous researches are mainly about the coefficients of the multiple feedback electromechanical ???? modulators. In the work presented here, a systematic design method for the feed forward ???? interfaces is proposed. Simulations show that utilizing the proposed method, feed forward and the optimized multiple feedback electromechanical sigma-delta modulators have almost the same SQNRs when a compensator pole is added to the feed forward structure. However, the feed forward structures have many advantages, so the proposed method is a promising alternative method for the multiple feedback structure.     

Outage-based design of robust Tomlinson–Harashima transceivers for the MISO downlink with QoS requirements

We consider a broadcast channel in which the base station is equipped with multiple antennas and each user has a single antenna, and we study the design of transceivers based on Tomlinson–Harashima precoders with probabilistic quality of service (QoS) requirements for each user, in scenarios with uncertain channel state information (CSI) at the transmitter. Each user's QoS requirement is specified as a constraint on the maximum allowed outage probability of the receiver's mean square error (MSE) with respect to a specified target MSE, and we demonstrate that these outage constraints are associated with constraints on the outage of the received signal-to-interference-plus-noise-ratio (SINR). We consider four different stochastic models for the channel uncertainty, and we design the downlink transceiver so as to minimize the total transmitted power subject to the satisfaction of the probabilistic QoS constraints. We present three conservative approaches to solving the resulting chance constrained optimization problems. These approaches are based on efficiently solvable deterministic convex design formulations that guarantee the satisfaction of the probabilistic QoS constraints. We also demonstrate how to apply these approaches in order to obtain computationally efficient solutions to some related design problems. Our simulations indicate that the proposed methods can significantly expand the range of QoS requirements that can be satisfied in the presence of uncertainty in the CSI.     

Systematic approach to the synthesis of continuous-time cascaded sigma–delta modulators

This paper deals with a systematic approach to the synthesis of continuous-time cascaded sigma–delta modulators. Based on a system-theoretical model, a detailed derivation of the digital cancelation filters for continuous-time cascaded architectures is presented in order to achieve maximum signal-to-noise ratio together with optimal anti-aliasing performance. By using the same model, an exact equation for the performance loss of any cascaded architecture is derived. The latter is due to the scaling for stability and given relative to an ideal high-pass filter of the overall modulator order. Finally, an analytical calculation of optimal scaling coefficients in between the stages is performed, resulting in a limited search-space for these coefficients. Theoretical results are verified by simulations.     

Noise analysis of a first-order thermal ΣΔ architecture for convective accelerometers

This paper presents the study of an original closed-loop conditioning approach for fully-integrated convective inertial sensors. The method is applied to an accelerometer manufactured on a standard CMOS technology using an auto-aligned bulk etching step. Using the thermal properties of the sensor, a first order sigma-delta modulator is built. This “electro-physical” modulator realizes an analog-to-digital conversion of the acceleration signal. Besides, the feedback mode of operation improves the sensor overall performance.     

Gate-leakage compensation scheme for programmable SI-DAC of ΣΔ modulator in deep sub-micron

A gate-leakage compensation scheme is proposed to solve the gate-leakage current issue caused by large-size current-source transistors in multi-bit switched-current (SI) DACs of the continuous-time ΣΔ modulator in deep sub-micron process without extra power consumption. To cover wide current range due to variable coefficients in different modes, the programmable SI-DAC architecture with 2-bit digital controlled unit cells is proposed. Implemented in 65 nm CMOS, the simulated results verify that the proposed scheme solves the gate-leakage issue and the modulator achieves tremendously high performance of 84.5 dB SQNDR and 94.6 dB SFDR with almost 14 and 19 dB improvement in SQNDR and SFDR, respectively.     

An integrated 0.38–6 GHz, 9–12 GHz fully differential fractional-N frequency synthesizer for multi-standard reconfigurable MIMO communication application

A wide-band fully differential fractional-N frequency synthesizer for multi-standard application is presented. The single fully differential LC–VCO with 28.5 % tuning rang and a set of dividers, quadrature self-mixer are designed to accomplish the multi-frequency bands with the frequency band from 0.38 to 6 GHz and from 9.0 to 12 GHz. It covers several wireless standards. A novel high isolation multiplexer is presented to achieve the frequency band selection. This chip was implemented with 65 nm CMOS technology and the maximum consumption is 20.05 mA from 1.2 V power supply. It occupies an active area of 1.5 mm². The measured typical phase noise of the frequency synthesizer is ?114.6 dBc/Hz from 1 MHz offset for 4.85 GHz output.     

Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers

Design and analysis of a Σ∆ modulator with a passive switched capacitor loop filter is presented. Design steps for optimum loop filter design for quantization noise suppression and thermal noise reduction is outlined. Design specifications for sampling clock phase noise, reference buffer and input buffer settling is analyzed. Presented design has a 2nd-order loop filter and uses only metal-metal capacitors and thin oxide digital transistors with no additional components occupying less than 0.1 mm² silicon area in 0.13 μm CMOS digital process. Measurement results show that the ADC achieves 80 dB peak SNR at a 100 kHz integration bandwidth with 1 pJ/sample conversion efficiency. With decimation filter power consumption of 0.22 mW at 104 MHz sampling rate, the ADC consumes only about 1 mA at 1.5 V for each channel.     

A 5th-order ΣΔ modulator with combination of op-Amp and CBSC circuit for ADSL applications

In this letter, a 5th-Order single-loop low distortion Sigma–Delta Modulator (SDM) is implemented with the combination of the comparator-based switched-capacitor (CBSC)-based and op-amp-based techniques for asymmetric digital subscriber line (ADSL) applications. This structure, which uses integrator (CBSC-based) and IIR filter (op-amp-based) concurrently, has relatively fewer feed-forward paths and modulator coefficients for sensitivity reduction to mismatch. To lower the power consumption of the modulator, the integrators are implemented with CBSC, the IIR filter block is implemented by single OTA, and a passive adder is used to realize the adder at the input of the 5-bit quantizer. The design purpose is minimizing the power consumption while the dynamic performance maintains high. As shown in the simulation result, for a 2-MHz signal bandwidth, the modulator achieves a dynamic range (DR) of 86.5 dB and a peak signal-to-noise and distortion ratio (SNDR) of 85 dB with an oversampling ratio of 8. In addition it consumes 18.75 mW from a 1.8-V power supply at 32 MS/s, which obtains a figure of merit of 1.6e−3.     

A model for concept evaluation in design––an application to mechatronics design of robot grippers

In this paper, an approach for the modelling of the evaluation process in the conceptual design phase is presented. During the design process, the generated candidate solutions are evaluated. The evaluation is achieved by calculating a score that is based on specific criteria that are presented as elements of a vector. Weight factors are applied to highlight the importance of each criterion. The formulation of the evaluation score is based on t-norm and averaging operators with the assumption that the universe of discourse of criteria is [0,1]. A discussion of the meaning of these operators and a comparative study of them is presented. As an application, the mechatronics design of robot grippers for handling fabrics is analysed. The elements of the mechatronics index are presented in terms of flexibility, intelligence and complexity. This index is formulated using the variety of the t-norms and averaging operators to show the weaks and strengths of each of them.     

A design of order-adjustable Σ∆ modulator for high performance micro-machined accelerometers

Sigma-delta modulation has been widely used in micro-machined accelerometers. Previous researches are mainly focused on increasing the order of the sigma-delta modulator for the mechanical sensor to improving the performance of the micro-machined accelerometers. These designs performed well in high resolution acceleration measurement, but they are insufficient in balancing the proof mass quickly while the micro-machined accelerometer is working. In this paper, the design of order-adjustable micro-machined accelerometer is proposed. It employs a mechanical sensor to balance the proof mass, and a fifth order MEMS accelerator to measure the acceleration with high resolution. Furthermore, this work shows an optimized design with a SQNR of 156.5 and 73.6 dB which can accurately measure the acceleration input and quickly balance the proof mass, respectively.     

New design of 3.2–4.8 GHz generator for multi-bands architecture of UWB communication

In this paper a new design of Ultra-Wide Band (UWB) generator is presented. This circuit is the most important block in multi-bands transmitter architecture of UWB communication system. The proposed UWB generator is composed of multi-bands voltage controlled oscillator (VCO), mixer and rectangular pulse generator which consist of ring oscillator, time delay and AND gate function. The UWB generator is based on multiplying the rectangular pulse envelope to a continuous sinusoidal wave in order to generate the UWB signal. This UWB generator circuit produces an output signal which is characterized by the bandwidth of 1600 MHz divided into three sub-bands of 528 MHz, centered at frequencies of 3.432, 3.96, 4.488 GHz and the limited Power Spectral Density (PSD) is −41.44 dBm/MHz. The maximum amplitude of UWB signal is 214 mV, the pulse is during of 3 ns and the pulse repetition period (PRP) is 32 ns. The power consumption is approximately equal to 26 mW at a voltage supply of 2.5 V. This topology is designed in CMOS 0.35 μm AMS process technology.     

Very large-scale neighborhood search algorithms for the design of service overlay networks

Service Overlay Networks (SONs) allow virtual operators to create and deploy value-added Internet services with Quality of Service guarantees, while leaving the underlying network infrastructure unchanged. The deployment of a SON can be very expensive, and hence its planning requires careful decisions, including the overlay nodes’ placement and the capacity provisioning of the access links that connect the end-users to the SON infrastructure.     

Modelling the current—voltage characteristic of a fluorescent lamp for computer-aided design

An empirical formula is presented for the voltage-current characteristics of a fluorescent lamp. The three parameters of the formula can easily be obtained from the measured characteristics of the fluorescent lamp without recourse to conventional curve-fitting techniques. By using this formula the analytical study of electronic circuits incorporating fluorescent lamps can be simplified.     

Computational design of low singlet–triplet gap all-organic molecules for OLED application

It was recently reported that external quantum efficiency in organic LEDs can be substantially enhanced when triplet excitons are harvested through upconversion by E-type delayed fluorescence in materials with small singlet–triplet energy gap ΔE_ST, based on donor–acceptor (DA) chromophores. Furthermore, organic solar cells (OSCs) might profit from such materials in order to reduce recombination losses. However, targeted design rules for such materials are missing up to now. In this paper, we follow a facile (TD-)DFT-based computational design concept by engineering the fragment frontier orbitals in DA systems. The calculations show that optimized systems with very small ΔE_ST in the range of kT can be achieved by balancing the energetic offset between fragment MOs as well as through the nature of the DA connector. Application in OLED will additionally require small non-radiative rates, which recommends large bandgap materials. Utilization in polymeric DA systems with small ΔE_ST in OSCs requires the full exploration of the chain length dependence of the respective oligomers.     

Comments on “A model-based design methodology for the development of mechatronic systems”

In the paper by Barbieri et al. (2014), a design methodology, based on the W life cycle process model, is presented and SysML is proposed as a tool to support the whole development process. In this letter, we discuss the presented approach, we point out technical errors and raise additional issues that might help in making the proposed approach applicable.     

Economics of “design for test” to remain competitive in the 90s

This article emphasizes the criticality of maximizing value adders and minimizing the costs of design for test (DFT) in order to remain competitive in ASIC manufacturing in the 90s.