高压熔断器的异常熔断原因探究

高压熔断器的使用时常会给电力系统带来较大的安全隐患,如果使用不当的话,电网的安全性也会受到威胁,本文针对异常熔断的原因展开分析,了解高压熔断器的特性,并且提出解决异常熔断的措施,以供参考.     

基于伏安曲线的熔断器熔断电流的无损检测

调节熔断器电流的同时测量熔断器两端的电压,获得待测熔断器的U-I曲线并计算出U-R曲线,对比两种曲线分析了熔断机理和规律,发现当熔断器的U-I曲线开始偏离直线时表示其即将熔断,此时所对应的电流可以较准确地表征待测熔断器的实际熔断电流。U-I曲线检测方法简便并且对待测样品几乎无损,实验表明经过该法检测合格的熔断器可以更安全可靠地工作。     

单层结构与双层结构保险丝熔断特性比对

贴片保险丝是一般电子产品中最常被用来作为电路上过电流或短路保护的元器件。保险丝会根据其熔断时间及耐脉冲能力来区分不同的熔断特性。各保险丝制造商往往选择不同的金属材料特性当作熔丝,结合适当的基体材料及设计结构制造出适合的熔断特性保险丝。目前市场上的低电压规格(≤63Vdc)贴片保险丝依据其熔丝的结构,基本上可以分为     

多层结构对有机电致发光器件性能的影响

将发光层进行多次堆叠,构造出有机电致发光器件.在堆叠过程中,改变各发光层厚度的相对比例,发现在总厚度相同、结构相同,而各发光层比例不同的条件下,器件呈现不同的发光特性.器件的电致发光光谱有着明显的变化,器件颜色由蓝光到近白光改变极其明显,器件的亮度和器件的效率也有不同程度的改变.     

片式熔断器和玻璃陶瓷用于低成本高性能的ESD保护

达到什么样的标准才是好的片式熔断器？快断、慢断、高抗浪涌熔断器之间的区别又是什么？除了压敏电阻、TVS,还有哪些ESD保护器件可供使用？他们之间的优缺点是什么？熔断器和ESD保护器件的技术发展趋势是什么？针对这些问题,《中国电子商情》合作伙伴电子元件技术网专访了AEM（控股）公司资深技术副总裁李向明博士。     

钝化层质量对高压功率器件可靠性的影响

针对钝化层质量对高压VDMOS器件可靠性的影响做了研究。通过流片生产中的产品遇到的实际问题,分析了高压VDMOS器件的钝化层可能存在的离子或者受热应力对器件可靠性的不良影响,并在实际工艺和芯片设计上作出了相应的改进,流片验证可靠性得到了有效的改善。     

原材料物理化学特性对多孔性PTC陶瓷结构与性能的影响

本文研究了以不同物理化学形态的含结晶水有机酸盐草酸氧钛钡为原料时，对多孔性ＰＴＣ陶瓷的结构与性能的影响；以及同时以不同结晶水含量的草酸氧钛钡为主原料时，二者分别对同一块多孔性ＰＴＣ陶瓷的不同结构特征、不同性能特征做出的不同贡献。     

PECVD淀积介质层对MOSFET性能的影响

通过对nMOS器件随天线比增加的阈值电压漂移、跨导变化,MOS电容在TDDB测试后的QBD退化分析来评估在RIE（Reactive Ion Etching）金属前PECVD-TEOS预淀积保护介质层的保护作用,实验结果表明此介质层没有起到足够的保护作用,反而会由于更长的等离子体工艺时间产生更严重的损伤问题。传统的电荷在硅片表面积累理论不足以解释此现象,本文从高能电子隧穿作用来分析此性能退化的原因。     

工艺参数对等离子弧沉积316L不锈钢形貌及组织的影响

以316L不锈钢粉末为原料,采用等离子弧沉积技术在高沉积速率下获得了致密无缺陷的单道试样。首先研究了沉积电流、扫描速度、送粉速度与沉积层高度、沉积层宽度、沉积角之间的关系,然后对沉积试样的微观组织和组成成分进行了检测与分析。结果表明:沉积角随着送粉速度的增大而增大,随着沉积电流的增大而减小;沉积角主要是锐角,有利于试样的沉积;沉积电流对沉积层宽度的影响最大,扫描速度对沉积层高度的影响最大,稀释率随着扫描速度的增大而减小,随着沉积电流的增大而增大,随送粉速度增大而减小;沉积试样成分均匀,凝固组织为奥氏体和铁素体。     

电极层对压电微悬臂梁动态性能的影响

采用解析方法就电极层对压电微悬臂梁动态性能的影响进行了研究,并得出结论:当弹性层、压电层与电极层的厚度比值较大时,可忽略电极层对压电悬臂梁横向位移及谐振频率的影响。当各层的厚度都在微纳米量级时,电极层的影响不容忽视;同时,微纳尺度下该解析方法的适用性还有待进一步研究。这些对微纳尺度下压电悬臂梁的设计及应用都有一定的指导作用。     

Effect of high voltage electric field on structure and property of PEDOT:PSS film

Low electrical conductivity of PEDOT:PSS film is to some extent a limit for its wide application. To solve this problem, the high voltage electric field was used to improve the film’s electrical conductivity and its effects on the film’s structure and properties were investigated. The PEDOT:PSS film was prepared on quartz substrate with spin coating. Visible light transmittance of the prepared film was tested with UV–Visible spectroscopy and chemical structure was measured with Fourier transform Raman spectroscopy (FIRM). The surface morphology was characterized with AFM, and electrical conductivity was measured with Hall effects measurement. The results showed that with the increase of the electric field, the electrical conductivity of PEDOT:PSS film was boosted rapidly at first, and then improved slowly when the electric field was above 200 kV/m. The film’s electrical conductivity improved more than 17 times in total from 0.51 × 10^–3 up to 8.92 × 10^–3 S/m. However, the film’s visible light transmittance decreased only a little with the increase of the electric field, not more than 3%. In addition, despite little change in the chemical structure of the PEDOT:PSS film, its surface roughness increased significantly with the increase of the electric field intensity.     

特高压平行双回线路熄弧措施的研究

特高压平行双回输电线路是电网的主要组成部分.本文从特高压平行双回线的HSGS工作流程入手,对特高压平行双回线路熄弧措施进行分析和研究.     

The influence of arc chamber wall material on arc gap dielectricrecovery voltage

The dielectric breakdown strength of an arcing contact gap after current zero was compared when using alumina, polyamide 6/6 (PA 6/6), and polyoxymethylene (POM) arc chamber wall materials. Plasma characteristics were obtained for each material by applying a reverse recovery voltage across the open contacts at a predetermined delay time after current zero. Ablation from each type of chamber wall material produced different plasma compositions each with different recovery voltage, arc voltage, and pressure characteristics. Tests were performed for an arcing current of 12 kA_p, for one half-cycle using symmetric AgW contacts. A thermal breakdown model along with an exponential curve fit to the measured results were used to obtain the initial holdoff voltage and plasma time constant for each material. PA 6/6 and POM had similar time constants with PA 6/6 having slightly better performance. Two types of breakdown mechanisms were identified-thermal and dielectric     

变电站高压设备分布式物理化结构模型

设计基于激光即时定位与地图构建(Simultaneous Localization And Mapping, SLAM)技术的变电站高压设备分布式物理化结构模型,精准获取高压设备位姿信息,有效建立高压设备分布式物理化结构模型。利用无人机搭载激光雷达传感器与惯性测量单元,扫描并测量施工建设中高压设备环境信息;利用激光SLAM技术依据激光雷达传感器的扫描信息,求解设备位姿信息;通过扩展卡尔曼滤波算法,融合惯性测量单元测量的设备姿态角信息;利用加权数据融合算法,融合位姿信息与姿态角信息,获取最终设备位姿信息;依据最终位姿信息,建立设备实景三维模型;通过建筑信息模型,建立设备的建筑信息模型(Building Information Modeling, BIM)模型;利用Revit软件,以自动关联方式,构造两个模型间的关联关系,获取设备分布式物理化结构模型。实验证明：该模型可精准获取设备位姿信息,有效建立清晰的分布式物理化结构模型;该模型可有效融合设备姿态角,提升姿态角测量曲线平滑度。     

A novel analytical model of the vertical breakdown voltage on impurity concentration in top silicon layer for SOI high voltage devices

A novel analytical model of the vertical breakdown voltage (V_{B , V} ) on impurity concentration (N_d ) in top silicon layer for silicon on insulator high voltage devices is first presented in this article. Based on an effective ionisation rate considering the multiplication of threshold energy ε_T in the electron, a new formula of silicon critical electric field E_{S , C} on N_d is derived by solving a 2D Poisson equation, which increases with the increase in N_d especially at higher impurity concentration, and reaches up to 68.8?V/µm with N_d  = 1 × 10¹⁷?cm^?3 and 157.2?V/µm with N_d  = 1 × 10¹⁸?cm^?3 from the conventional about 30?V/µm, respectively. A new physical concept of critical energy ε_B is introduced to explain the mechanism of variable high E_{S , C} with heavy impurity concentration. From the E_{S , C} , the expression of V_{B , V} is obtained, which is improved with the increasing N_d due to the enhanced E_{S , C}. V_{B , V} with a dielectric buried layer thickness (t_I ) of 2?µm increases from 428?V of 1 × 10¹⁷?cm^?3 to 951?V of 1 × 10¹⁸?cm^?3. The dependence of N_d and top silicon layer thickness (t_S ) for an optimised device is discussed. 2D simulations and some experimental results are in good agreement with the analytical results.     

一种新型高压Triple RESURF SOI LDMOS

提出了一种新型Triple RESURF SOI LDMOS结构,该结构有一个Ｐ型埋层。首先,耗尽层能够在Ｐ型埋层的上下同时扩展与Triple RESURF机理相同,使得漂移区浓度提高,导通电阻降低。其次,当漂移区浓度较高时,Ｐ型埋层起到了降低体内电场的作用,并能够提高漏端纵向电场使得其电场分布更加均匀从而耐压增加。Triple RESURF结构在SOI LDMOS中首次提出。在６微米厚的SOI层以及２微米厚的埋氧层中获得了耐压300V的Triple RESURF SOI LDMOS,其导通电阻从Double RESURF SOI LDMOS的17.2mΩ.cm2降低到13.8mΩ.cm2。当外延层厚度增加时, Triple RESURF结构的效果更加明显,在相同耐压下,相对于Double RESURF,该结构能够在400V和550V的SOI LDMOS中分别降低29%和38%的导通电阻。     

A new high voltage SOI LDMOS with triple RESURF structure

A novel triple RESURF（T-resurf） SOI LDMOS structure is proposed.This structure has a P-type buried layer.Firstly,the depletion layer can extend on both sides of the P-buried layer,serving as a triple RESURF and leading to a high drift doping and a low on-resistance.Secondly,at a high doping concentration of the drift region, the P-layer can reduce high bulk electric field in the drift region and enhance the vertical electric field at the drain side,which results in uniform bulk electric field distributions and an enhanced BV.The proposed structure is used in SOI devices for the first time.The T-resurf SOI LDMOS with BV = 315 V is obtained by simulation on a 6μm-thick SOI layer over a 2μm-thick buried oxide layer,and its R_sp is reduced from 16.5 to 13.8 mΩ·cm² in comparison with the double RESURF（D-resurf） SOI LDMOS.When the thickness of the SOI layer increases, T-resurf SOI LDMOS displays a more obvious effect on the enhancement of BV²/R_on.It reduces R_sp by 25%in 400 V SOI LDMOS and by 38%in 550 V SOI LDMOS compared with the D-resurf structure.     

酞菁铜缓冲层对有机太阳能电池开路电压的影响

用p型有机半导体材料酞菁铜作为阴极缓冲层制作了器件结构为氧化铟锡/酞菁锌/碳六十/酞菁铜/铝的有机小分子太阳能电池, 对器件进行电学测量发现酞菁铜缓冲层的厚度对器件的开路电压有明显影响.基于半导体器件物理分析了光照下测量得到的电流-电压曲线, 由拟合结果得到的器件参数表明高理想因子导致了器件开路电压升高, 其原因为器件的输运特性不只受酞菁锌与碳六十形成的p-n结影响, 还与酞菁铜缓冲层与铝电极形成的肖特基接触有关.研究表明在有机太阳能电池器件中引入一个合适的缓冲层/阴极肖特基结可以提高器件的开路电压.     

具有缓冲层和N型埋层的高压兼容Bi-CMOS工艺的超结LDMOS

A novel buffer super-junction （S J） lateral double-diffused MOSFET （LDMOS） with an N-type buried layer （NB） is proposed. An N- buffer layer is implemented under the SJ region and an N-type layer is buried in the P substrate. Firstly, the new electric field peak introduced by the p-n junction of the P substrate and the N-type buried layer modulates the surface electric field distribution. Secondly, the N-buffer layer suppresses the substrate assisted depletion effect. Both of them improve the breakdown voltage （BV）. Finally, because of the shallow depth of the SJ region, the NB buffer SJ-LDMOS is compatible with Bi-CMOS technology. Simulation results indicate that the average value of the surface lateral electric field strength of the NB buffer SJ-LDMOS reaches 23 V/μm at 15/μm drift length which results in a BV of 350 V and a specific on-resistance of 21 mΩ·cm2.     

Super junction LDMOS with enhanced dielectric layer electric field for high breakdown voltage

The lateral super junction(SJ) power devices suffer the substrate-assisted depletion(SAD) effect,which breaks the charge balance of SJ resulting in the low breakdown voltage(BV).A solution based on enhancing the electric field of the dielectric buried layer is investigated for improving the BV of super junction LDMOSFET (SJ-LDMOS).High density interface charges enhance the electric field in the buried oxide(BOX) layer to increase the block voltage of BOX,which suppresses the SAD effect to achieve the charge balance of SJ.In order to obtain the linear enhancement of electric field,SOI SJ-LDMOS with trenched BOX is presented.Because the trenched BOX self-adaptively collects holes according to the variable electric field strength,the approximate linear charge distribution is formed on the surface of the BOX to enhance the electric field according to the need.As a result,the charge balance between N and P pillars of SJ is achieved,which improves the BV of SJ-LDMOS to close that of the idea SJ structure.