Performance Modeling of Low-$k$/Cu Interconnects for 32-nm-Node and Beyond

Challenges and issues with the scaling of low-$k$/Cu interconnects in ultra-large-scale integration (ULSI) devices are reviewed, and the performance of interconnects is featured by considering the effect of the resistance and capacitance per unit interconnect length or the minimum grid length. The grid-scaled resistance–capacitance (GSRC) model is proposed to compare the interconnect performance at various technology nodes. Introduction of low-$k$ films to reduce the line capacitance improves the per-grid value of the resistance–capacitance product, however, the abrupt increment of the line resistivity due to the small-size effect consumes the benefit of the capacitance beyond 32-nm-node. We also discuss power consumption in interconnects with different low- $k$ structures based on experimental works. Continuous reduction of effective $k$-value $(K_{ rm eff})$ is needed to reduce the active power consumption. The way to reduce the interconnect resistance while keeping the interconnect reliability high is a key challenge, particularly for deeply scaled-down ULSIs.      

Modeling and Analysis of On-Chip Single and H-tree Distributed RLC Interconnects

This paper presents novel methods for modeling and analysis of on-chip Single and H-tree distributed resistance inductance capacitance interconnects. The matrix pade-type approximation and scaling and squaring methods are employed for the numerical estimation of delay in single interconnect, and H-tree interconnects. The proposed models, which are based on these methods, provide rational function approximation for obtaining a passive interconnect model. Multiple single input single output model approximated transfer functions are developed for H-tree interconnects structure. With the equivalent reduced order lossy interconnect transfer functions, finite ramp responses are obtained, and line delay is estimated for various line lengths, input ramp rise times, source resistances, parasitic capacitances and load capacitances. In order to demonstrate the accuracy of proposed models, the estimated 50 % delay values are compared with the standard HSPICE W-element model and are found to be in good agreement. The proposed models worst case 50 % delay errors of single interconnect are 0.27 and 0.24 % respectively, while the worst case 50 % delay errors of H-tree structure are 5.73 and 3.94 % respectively.     

Tradeoff between interconnect capacitance and RC delay variationsinduced by process fluctuations

This paper describes the influence of the process fluctuations such as the critical dimension (CD) variation upon the interconnect capacitance C and RC delay. It is found that there is a tradeoff between C and RC delay variations because of the fringing capacitance. An interconnect design guideline to reduce C and/or RC delay variations is proposed. Also, C and RC delay variations for Cu interconnect are discussed     

多层空气隙Cu互连结构耦合电容的优化

随着超大规模集成电路特征尺寸不断缩小,多层cu互连之间的RC延迟成为一个越来越严重的问题.由于低介电常数(low-k)材料配合空气隙(air gap)结构可用于降低Cu互连导线间的耦合电容从而改善RC延迟特性,建立了单层和多层空气隙Cu互连结构的有限元分析模型,以研究空气隙结构尺寸与互连介质等效介电常数的关系.结果表明,在单层空气隙Cu互连结构中,通过增加互连导线间空气隙的结构尺寸可以减小Cu互连结构中的耦合电容,进而改善RC延迟特性;在多层空气隙Cu互连结构中,通过改变IMD和ILD中空气隙的尺寸结构可以得到RC延迟性能优化的多层空气隙Cu互连结构.     

A multilevel parasitic interconnect capacitance modeling andextraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays     

Compact distributed RLC interconnect models. I. Single linetransient, time delay, and overshoot expressions

Novel compact expressions that describe the transient response of a high-speed distributed resistance, inductance, and capacitance (RLC) interconnect are rigorously derived with on-chip global interconnect boundary conditions. Simplified expressions enable physical insight and accurate estimation of transient response, time delay, and overshoot for high-speed global interconnects with the inclusion of inductance     

三维闪存中基于钨互连的空气隙结构的制备工艺

将空气隙应用于逻辑器件后段金属互连线中可以有效降低互连线间的寄生电容,提升电路信号传输速度,但制备过程仍具有一定的困难。基于三维闪存(3D NAND)中后段(BEOL)W的自对准双重图形化(SADP)工艺,利用湿法刻蚀的方法在W化学机械平坦化(CMP)之后去除SiO_2介质层,然后再利用化学气相淀积(CVD)法淀积一层台阶覆盖率较低的介质在金属互连线层内形成空气隙。采用空气隙结构代替原来的SiO_2介质层可降低约37.4%的寄生电容,且薄膜的台阶覆盖率会进一步降低电容。TCAD仿真和电性能测试结果表明,采用该方法制备的空气隙结构可降低互连延迟。     

互连线间容性串扰对延迟的影响

集成电路的性能越来越受到互连线间寄生效应的影响,特别是耦合电容的容性串扰,容性串扰引起互连线跳变模式相关的延迟。文中从E lm ore de lay定义的角度推导了互连线受同时跳变的阶跃信号激励时开关因子的大小,分析了互连线受非同时跳变的阶跃信号激励时耦合电容对互连线延迟的影响,给出了不同激励时的受害线延迟计算方法。分析表明,开关因子为0和2不能描述耦合电容对受害线延迟影响的下上限。H sp ice模拟结果证明了分析计算的准确性。     

Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing

Every new VLSI technology generation has resulted in interconnects increasingly limiting the performance, area, and power dissipation of new processors. Subsequently, it is necessary to devise efficient interconnect design techniques to reduce the impact of VLSI interconnects on overall system design. New optimizations of a wave-pipelined multiplexed (WPM) interconnect routing circuit are described in this paper. These WPM circuits can be used with current interconnect repeater circuits to further reduce interconnect delay, interconnect area, transistor area, and/or power dissipation. For example, new area constrained WPM circuit optimizations illustrate that the interconnect circuit power can be reduced by 26% or the interconnect performance can be improved by 74%. Moreover, in both these cases, because a significant number of repeaters are eliminated, the transistor area can reduce by 41% or 29%, respectively. Finally, the tolerance of WPM circuits to crosstalk noise, power supply noise, clock skew, and manufacturing variations is also presented. This study of tolerance levels defines the conditions under which the WPM circuit will function correctly, and it is shown in this paper for the first time that WPM circuits are robust enough to operate with variability that can be encountered in deep submicrometer technologies.     

Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects

The proliferation of portable electronics has imposed a pressing need on design of low power circuits. Sub threshold circuits are the ideal candidate to quench the demand of ultra-low power. However, degraded performance and exacerbated variability are the major concerns of sub threshold circuits. Furthermore, the global interconnects significantly affects the performance and power dissipation in sub threshold circuits. The obvious reason is the increased capacitance of long global interconnects which is further augmented with increase in sub threshold CMOS driver resistance. This paper explores the performance of sub threshold global interconnect with six different configurations of DG FinFET driver circuit viz. FinFET SG, TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG. Performance analysis indicates that FinFET SG configuration exhibits 60.7, 0.8, 2.3, 37 and 40% better energy efficiency compared to TGIG, THYBRID, TGSG, TPIGNSG and TPSGNIG respectively at 225 mV supply voltage. Furthermore, the crosstalk analysis results shows that the glitch amplitude in TGSG driven interconnect and THYBRID driven interconnect is increased by 89.6 and 74% respectively compared to FinFET SG driven interconnect. This work also investigates the suitability of conventional buffer insertion technique for enhancing the performance of DG FinFET driven sub threshold global interconnects. The buffered and un-buffered interconnect shows comparable delay, PDP and EDP in sub threshold region. Furthermore, Monte Carlo analysis results indicate that spread in delay exhibited by FinFET SG driven un-buffered interconnect circuit is lesser by 25% compared to FinFET SG driven buffered circuit in sub threshold region.

     

Through-silicon-via insertion for performance optimization in three-dimensional integrated circuits

Through-silicon-via (TSV) interconnect is one of the main technologies for three-dimensional integrated circuits production (3-D ICs). Based on a parasitic parameters extraction model, first order expressions for the TSV resistances, inductances, and capacitance as functions of physical dimension and material characteristic are derived. Analyzing the impact of TSV size and placement on the interconnect timing performance and signal integrity, this paper presents an approach for TSV insertion in 3D ICs to minimize the propagation delay with consideration to signal reflection. Simulation results in multiple heterogeneous 3D architectures demonstrate that our approach in generally can result in a 49.96% improvement in average delay, a 62.28% decrease in the reflection coefficient, and the optimization for delay can be more effective for higher non-uniform inter-plane interconnects. The proposed approach can be integrated into the TSV-aware design and optimization tools for 3-D circuits to enhance system performance.     

Interconnect design strategy: structures, repeaters and materialswith strategic system performance analysis (S2PAL) model

In this paper, we propose a novel methodology for scheming an interconnect strategy, such as what interconnect structure should be taken, how repeaters should be inserted, and when new metal or dielectric materials should be adopted. In the methodology, the strategic system performance analysis model is newly developed as a calculation model that predicts LSI operation frequency and chip size with electrical parameters of transistors and interconnects as well as circuit configuration. The analysis with the model indicates that interconnect delay overcomes circuit block cycle time at a specific length; D_c-cross. Here tentatively, interconnects shorter than D_c-cross are called local interconnects, and interconnects longer than that as global ones. The cross-sectional structures for local and global tiers are optimized separately. We also calculate global interconnect pitch and the chip size enlarged by the global interconnect pitch and the inserted repeaters, and then estimate the effectiveness of introducing new materials for interconnects and dielectrics     

Modelling interconnects with surface roughness

Interconnect modelling is playing crucial role in the integrated circuit design verification since the performance success of design depends on interconnects for today's ICs. For accurate modelling it is more important to take into account all the physical effects with the progresses in technology. One such aspect is roughness on the interconnect surfaces which is arising due to various processes used for fabricating them. In this paper we present model and simulation results for interconnect capacitance, resistance and maximum electric field for interconnects with rough surface.     

Global interconnect width and spacing optimization for latency, bandwidth and power dissipation

This paper addresses a novel methodology optimizing global interconnect width and spacing for International Technology Roadmap for Semiconductors technology nodes. Global interconnects with and without buffer insertion are considered. The effects of the width and spacing of global interconnects on performance, such as delay, bandwidth, total repeater area and energy dissipation, are analyzed. The product of delay and bandwidth is used as the figure of merit for simultaneous short latency and large bandwidth and the proposed methodology can optimize global interconnects for the maximal figure of merit. It is demonstrated that buffers should not be inserted in global interconnects if interconnect length is shorter than a critical length, which is a constant for a given technology. For global interconnects with buffer insertion, the optimal width and spacing have analytical expressions and are constants for a given technology. For global interconnects without buffer insertion, the optimal width and spacing are dependent on both the technology parameters and interconnect length and can be computed numerically.     

Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects

Metallic carbon nanotubes (CNTs) have received much attention for their unique characteristics as a possible alternative to Cu interconnects in future ICs. Until this date, while almost all fabrication efforts have been directed toward multiwalled CNT (MWCNT) interconnects, there is a lack of MWCNT modeling work. This paper presents, for the first time, a detailed investigation of MWCNT-based interconnect performance. A compact equivalent circuit model of MWCNTs is presented for the first time, and the performance of MWCNT interconnects is evaluated and compared against traditional Cu interconnects, as well as Single-Walled CNT (SWCNT)-based interconnects, at different interconnect levels (local, intermediate, and global) for future technology nodes. It is shown that at the intermediate and global levels, MWCNT interconnects can achieve smaller signal delay than that of Cu interconnects, and the improvements become more significant with technology scaling and increasing wire lengths. At 1000- global or 500- intermediate level interconnects, the delay of MWCNT interconnects can reach as low as 15% of Cu interconnect delay. It is also shown that in order for SWCNT bundles to outperform MWCNT interconnects, dense and high metallic-fraction SWCNT bundles are necessary. On the other hand, since MWCNTs are easier to fabricate with less concern about the chirality and density control, they can be attractive for immediate use as horizontal wires in VLSI, including local, intermediate, and global level interconnects.     

Timing-driven via placement heuristics for three-dimensional ICs

The dependence of the interconnect delay on the interplane via location in three-dimensional (3-D) ICs is investigated in this paper. The delay of these interconnects can be significantly decreased by optimally placing the interplane vias. The via locations that minimize the propagation delay of two-terminal interconnects consisting of multiple interplane vias under the distributed Elmore delay model are determined. For interconnect trees, the interplane via locations that minimize the summation of the weighted delay of the sinks of the tree are also determined. For these interconnect structures, the interplane via locations are obtained both through geometric programming and near-optimal heuristics. Placement constraints are imposed such that the path is negligibly affected. The proposed heuristics are used to implement efficient algorithms that exhibit lower computational times as compared to general optimization solvers with negligible loss of optimality. Various interplane via placement scenarios are considered. Simulation results indicate delay improvements for relatively short point-to-point interconnects of up to 32% with optimally placed interplane vias. For interconnect trees, the maximum improvement in delay for optimally placed interplane vias is 19%. The proposed algorithms can be integrated into a design flow for 3-D circuits to enhance placement and routing where timing is a primary design criterion.     

工艺变化下互连线分布参数随机建模与延迟分析

随着超大规模集成电路制造进入深亚微米和超深亚微米阶段,电路制造过程中的工艺变化已经成为影响集成电路互连线传输性能的重要因素.文中引入高斯白噪声建立了互连线分布参数的随机模型,并提出基于Elmore延迟度量的工艺变化下的互连延迟估计式;通过简化工艺变化量与互连线参数之间的关系式,对延迟一阶变化量与二阶变化量进行了分析,给出一般工艺变化下互连延迟的统计特性计算方法;另,针对线宽工艺变化推导出互连延迟均值与方差的计算公式.最后通过仿真实验对工艺变化下互连线延迟分析方法及其统计特性计算公式的有效性进行了验证.     

Monolayer metallic nanotube interconnects: promising candidates for short local interconnects

Mono- or bi-layer metallic single-wall carbon nanotube interconnects have lateral capacitances more than four times smaller than those of copper interconnects. The resistance and time-of-flight of these monolayer nanotubes would be larger than that of copper interconnects. For short lengths, however, driver resistance is quite dominant, and latency is determined by interconnect capacitance. Monolayer nanotube interconnects are therefore promising candidates for local interconnects. The average capacitance per unit length of these nanotube interconnects can be 50% smaller than that of copper interconnects and that leads to significant saving in power dissipation.     

Minimization of delay and crosstalk in high-speed VLSIinterconnects

Design optimization of time responses of high-speed VLSI interconnects modeled by distributed coupled transmission line networks is presented. The problem of simultaneous minimization of crosstalk, delay and reflection is formulated into minimax optimization. Design variables include physical/geometrical parameters of the interconnects and parameters in terminating/matching networks. A recently published simulation and sensitivity analysis technique for multiconductor transmission lines is expanded to directly address the VLSI interconnect environment. The new approach permits efficient physical/geometrical oriented interconnect design using exact gradient based minimax optimization. Examples of interconnect optimization demonstrate significant reductions of crosstalk, delay, distortion and reflection at all vital connection ports. The technique developed is an important step towards optimal design of circuit interconnects for high-speed digital computers and communication systems     

A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability

This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k<2.7) interconnects for high-performance and low-power applications of a 0.13 μm generation. Aggressive design rules, 0.11 μm gate transistor and 2.2 μm² six-transistor SRAM cell are realized by using KrF 248 nm lithography, optical proximity effect correction, and gate-shrink techniques. Eight-level interconnects are fabricated with seven level of Cu/VLK interconnect and one level of Al/SiO₂ interconnect. Drain current of 0.67 and 0.28 mA/μm are realized for nMOSFET and pMOSFET with 0.11 μm gate, respectively. Propagation delay of two input NAND with the Cu/VLK interconnect is estimated. The delay is improved by more than 70%, compared to 0.18 μm CMOS technology with Cu/FSG interconnects. Functional 288 kbit SRAM circuit is demonstrated with 2.2 μm² cell and Cu/VLK interconnect.