Temperature dependent current–voltage (I–V) characteristics of Au/n-Si (1 1 1) Schottky barrier diodes with PVA(Ni,Zn-doped) interfacial layer

Current–voltage (I–V) characteristics of Au/PVA/n-Si (1 1 1) Schottky barrier diodes (SBDs) have been investigated in the temperature range 80–400 K. Here, polyvinyl alcohol (PVA) has been used as interfacial layer between metal and semiconductor layers. The zero-bias barrier height (Φ_B0) and ideality factor (n) determined from the forward bias I–V characteristics were found strongly dependent on temperature. The forward bias semi-logarithmic I–V curves for different temperatures have an almost common cross-point at a certain bias voltage. The values of Φ_B0 increase with the increasing temperature whereas those of n decrease. Therefore, we have attempted to draw Φ_B0 vs. q/2kT plot in order to obtain evidence of a Gaussian distribution (GD) of the barrier heights (BHs). The mean value of BH and standard deviation (σ₀) were found to be 0.974 eV and 0.101 V from this plot, respectively. Thus, the slope and intercept of modified vs. q/kT plot give the values of and Richardson constant (A^?) as 0.966 eV and 118.75 A/cm²K², respectively, without using the temperature coefficient of the BH. This value of A^* 118.75 A/cm²K² is very close to the theoretical value of 120 A/cm²K² for n-type Si. Hence, it has been concluded that the temperature dependence of the forward I–V characteristics of Au/PVA/n-Si (1 1 1) SBDs can be successfully explained on the basis of the Thermionic Emission (TE) theory with a GD of the BHs at Au/n-Si interface.     

Analysis of interface states and series resistance of MIS Schottky diodes using the current-voltage (I-V) characteristics

The purpose of this paper is to analyze interface states in Al/SiO₂/p-Si (MIS) Schottky diodes and determine the effect of SiO₂ surface preparation on the interface state energy distribution. The current-voltage (I-V) characteristics of MIS Schottky diodes were measured at room temperature. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_B) values of 1.537 and 0.763 eV, respectively, were obtained from a forward bias I-V plot. In addition, the density of interface states (N_ss) as a function of (E_ss-E_v) was extracted from the forward bias I-V measurements by taking into account both the bias dependence of the effective barrier height (Φ_e), n and R_s for the MIS Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. In addition, the values of series resistance (R_s) were determined using Cheung’s method. The I-V characteristics confirmed that the distribution of N_ss, R_s and interfacial insulator layer are important parameters that influence the electrical characteristics of MIS Schottky diodes.     

Studies on vacuum deposited p-ZnTe/n-CdTe heterojunction diodes

The present paper reports the fabrication and detailed electrical characterization of p-ZnTe/n-CdTe heterojunction diodes prepared by vacuum deposition method. The possible conduction mechanisms of the heterojunction diode were determined by analyzing the I-V characteristics. The C-V characteristics of the heterojunction diodes were studied to determine the barrier height, carrier concentration and thickness of the depletion region in the heterojunction. A theoretical band diagram of the heterojunction was drawn based on Anderson’s model.     

Electrical characteristics of high performance Au/n-GaN schottky diodes

Au/n-GaN Schottky diodes with the Au electrode deposited at low temperature (LT=77K) have been studied. In comparison, the same chip of GaN epitaxial layer was also used for room temperature Schottky diodes. The low temperature Schottky diodes exhibit excellent performance. Leakage current density as low as 2.55×10⁻¹¹ A·cm⁻² at −2.5 V was obtained in the LT Schottky diodes. The linear region in the current-voltage curve at forward bias extends more than eight orders in current magnitude. Current-voltage-temperature measurements were carried out to study the characteristics of the LT Schottky diodes. A typical barrier height of about 1.32 eV for the LT diode, which is the highest value ever reported, was obtained. The obvious enhancement in electrical performance makes the LT processing a very promising technique for GaN device application although the detailed mechanisms for the LT Au/n-GaN Schottky diodes are still under investigation.     

Thermally annealed Ni/n-GaAs(Si)/In Schottky barrier diodes

We have identically prepared as many as eight Ni/n-GaAs/In Schottky barrier diodes (SBDs) using an n-type GaAs substrate with a doping density of about 7.3 × 10¹⁵ cm⁻³. The thermal stability of the Ni/n-GaAs/In Schottky diodes has been investigated by means of current-voltage (I-V) techniques after annealed for 1 min in N₂ atmosphere from 200 to 700 °C. For Ni/n-GaAs/In SBDs, the Schottky barrier height Φ_b and ideality factor n values range from 0.853 ± 0.012 eV and 1.061 ± 0.007 (for as-deposited sample) to 0.785 ± 0.002 eV and 1.209 ± 0.005 (for 600 °C annealing). The ideality factor values remained about unchanged up to 400 °C annealing. The I-V characteristics of the devices deteriorated at 700 °C annealing.     

Effect of annealing temperature on the electrical characteristics of Platinum/4H-SiC Schottky barrier diodes

Pt/4H-SiC Schottky barrier diodes have been fabricated to investigate the effect of annealing on the electrical characteristics of the fabricated devices. The parameters such as barrier height, ideality factor and donor concentration were deduced from the current–voltage (I–V) and the capacitance–voltage (C–V) measurements at room temperature. Diodes showed non-ideal behaviour like high value of ideality factor and lower value of barrier height. A barrier height of 1.82?eV was obtained from C–V measurements and it was 1.07?eV when obtained from the I–V measurements with ideality factor 1.71 for as-deposited diodes at room temperature. The diodes, therefore, were annealed in the temperature range from 25°C to 400°C to observe the effect of annealing temperature on these parameters. Schottky barrier height and ideality factors were found to be temperature-dependent. After rapid thermal annealing upto 400°C, a barrier height of 1.59?eV from C–V measurements and the value of 1.40?eV from I–V measurements with ideality factor 1.12 were obtained. Barrier heights deduced from C–V measurements were consistently larger than those obtained from I–V measurements. To come to terms with this discrepancy, we re-examined our results by including the effect of ideality factor in the expression of the barrier height. This inclusion of ideality factor results in reasonably good agreement between the values of barrier height deduced by the above two methods. We believe that these improvements in the electrical parameters result from the improvement in the quality of interfacial layer.     

Carrier transport and related phenomena in MOS devices

Silicon-based devices are currently the most attractive group because they are functioning at room temperature and can be easily integrated into conventional silicon microelectronics. There are many models and simulation programs available to compute CV curves with quantum correction [Choi C-H, Wu Y, Goo JS, Yu Z, Dutton RW. IEEE Trans on Electron Devi 2000; 47(10): 1843; Croci S, Plossu C, Burignat S. J Mater Sci Mater Electron 2003; 14: 311; Soliman L, Duval E, Benzohra M, Lheurette E, Ketata K, Ketata M. Mater Sci Semicond Process 2001; 4: 163]. This work deals with the simulation of electron transfer through SiO₂ barrier of metal–oxide–semiconductor structure (MOS). The carrier density is given by a self consistent resolution of Schrödinger and Poisson equations and then the MOS capacitance is deduced and compared with results available in literature. As it is well known, the MOS capacitance–voltage profiling provides a simple determination of structure parameters. The extracted tunnel oxide thickness and substrate doping are compared with those used in the simulation. For the purpose to investigate the electron tunnelling through the barrier, we have used the transfer matrix approach. Using I–V simulations, we have shown that the traps in SiO₂ matrix have a drastic influence on electron tunnelling through the barrier. The trap-assisted contribution to the tunnelling current is included in many models [Maserjian J, Zamani N. J Appl Phys 1982; 53(1): 559; Houssa M, Stesmans A, Heyns MM. Semicond Sci Technol 2001; 16: 427; Aziz A, Kassmi K, Kassmi Ka, Olivie F. Semicond Sci Technol 2004; 19: 877; Wu You-Lin, Lin Shi-Tin. IEEE Trans Dev Mater Reliab 2006; 6(1): 75; Larcher L. IEEE Trans Electron Dev 2003; 50(5): 1246]; this is the basis for the interpretation of stress induced leakage current (SILC) and breakdown events. Memory effect becomes typical for this structure. We have studied the I–V dependence with trap parameters.     

Temperature dependence of Schottky diode characteristics prepared with photolithography technique

A Richardson constant (RC) of 8.92 Acm^?2K^?2 from the conventional Richardson plot has been obtained because the current–voltage data of the device quite well obey the thermionic emission (TE) model in 190–320 K range. The experimental nT versus T plot of the device has given a value of T₀ = 7.40 K in temperature range of 160–320 K. The deviations from the TE current mechanism at temperatures below 190 K have been ascribed to the patches introduced by lateral inhomogeneity of the barrier heights. Therefore, an experimental RC value of 7.49 A(cmK)^?2 has been obtained by considering Tung’s patch model in the temperature range of 80–190 K. This value is in very close agreement with the known value of 8.16 Acm^?2K^?2 for n-type GaAs.     

Improved Schottky Contacts on <Emphasis Type="Italic">n</Emphasis>-Type 4H-SiC Using ZrB<Subscript>2</Subscript> Deposited at High Temperatures

We report on improved electrical properties and thermal stability of ZrB₂ Schottky contacts deposited on n-type 4H-SiC at temperatures between 20°C and 800°C. The Schottky barrier heights (SBHs) determined by current-voltage measurements increased with deposition temperature, from 0.87 eV for contacts deposited at 20°C to 1.07 eV for those deposited at 600°C. The Rutherford backscattering spectroscopy (RBS) spectra of these contacts revealed a decrease in oxygen peak with an increase in the deposition temperature and showed no reaction at the ZrB₂/SiC interface. These results indicate improved electrical and thermal properties of ZrB₂/SiC Schottky contacts, making them attractive for high-temperature applications.     

Comparative study of quasi-static and normal capacitance–voltage characteristics in amorphous Indium-Gallium-Zinc-Oxide thin film transistors

Capacitance-voltage (C-V) characteristics of amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) are comparatively investigated with two different measurement configurations. Normal gate-to-source/drain (S/D) C-V and quasi-static C-V curves are employed to characterize physical mechanisms with equivalent circuit models for a-IGZO TFTs. The difference between the normal C-V and the quasi-static C-V (QSCV) characteristics is investigated by the dependence on the gate voltage (V_G), measurement configuration, and optical illumination. The discrepancy is analyzed to be due to a high hole barrier in the S/D contact region and a slow response of active bulk charges (Q_loc and Q_free) in the a-IGZO active layer.     

基于肖特基二极管的太赫兹二倍频器设计

固态倍频器是太赫兹源应用中的关键器件,如何利用非线性器件提高太赫兹倍频器件的效率是设计太赫兹固态电路的关键。本文介绍了利用肖特基二极管非线性特性设计固态太赫兹二倍频器的2种方法,即采用直接阻抗匹配和传输模式匹配设计了2种不同拓扑结构的170 GHz二倍频器,针对设计的结构模型,分别进行三维有限元电磁仿真和非线性谐波平衡仿真。仿真结果表明,在17 dBm输入功率的驱动下,倍频器在160 GHz~180 GHz输出频率范围内,倍频效率在15%左右,输出功率大于7 mW。最后对2种方法设计的倍频器结构进行了简单对比和分析,为今后太赫兹倍频研究和设计提供仿真方法。     

一种制备Au/n-Al0.3Ga0.7N横向肖特基二极管的方法

用MOCVD生长未掺杂n-Al0.3Ga0.7N制备了MSM结构紫外探测器,并通过电击穿MSM右边肖特基势垒而制成了横向肖特基二极管.器件在零偏电压处的背景光电流为87.3 pA.从器件的室温I-V特性曲线计算出理想因子n、零偏势垒高度B0和串联电阻RS分别为1.99、0.788 eV和10.2 kΩ.器件在305 nm波长处有陡峭的截止边,300 nm峰值波长处电流响应率为0.034 A/W.     

Precise determination of metal effective work function and fixed oxide charge in MOS capacitors with high-κ dielectric

Effective metal work function, Φ_m,eff, and oxide charge, Q_ox, were determined on MOS capacitors with slanted high-κ dielectric. Φ_m,eff and Q_ox were extracted using flat-band voltage shift versus equivalent oxide thickness data, both deduced from the capacitance–voltage measurements. Slanted HfSiO_x dielectric (initial thickness was 9 nm) was prepared by gradual etching in HF-based solution. As a metal electrode, thin Ru-films were deposited by MOCVD-derived technique—Atomic Vapor Deposition^® on the slanted HfSiO_x as well as SiO₂ dielectrics. The Φ_m,eff of Ru was found to be 4.74 and 4.81 eV for Ru/HfSiO_x and Ru/SiO₂ gate stacks, respectively. Ultraviolet photoelectron spectroscopy yields the work function of 4.62 eV in agreement with the capacitance–voltage data. We also studied the I–V characteristics of the Ru/HfSiO_x/Si MOS capacitors. The barrier height was found to be constant within the HfSiO_x bulk.