Fabrication and characterization of 11-kV normally off 4H-SiC trenched-and-implanted vertical junction FET

This letter reports the first demonstration of 101 kV trenched-and-implanted normally off 4H-SiC vertical junction field-effect transistor (TI-VJFET) with a 120 /spl mu/m /spl sim/4.9/spl times/10/sup 14/ cm/sup -3/-doped drift layer. Blocking voltages (V/sub B/) of 10 kV to 11 kV have been measured. The best specific on-resistance (R/sub SP/_/sub ON/) normalized to source active area has been determined to be 130 m/spl Omega//spl middot/cm/sup 2/. Three-dimensional computer modeling including current spreading effect shows that the TI-VJFET would have a specific resistance of 168 m/spl Omega//spl middot/cm/sup 2/ if it is scaled up substantially in size.     

1677 V, 5.7 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC BJTs

This letter reports the development of a high-performance power 4H-SiC bipolar junction transistor (BJT) with, simultaneously, a high blocking voltage and a low specific on-resistance (R/spl I.bar//sub ON/). A single BJT cell with an active area of 0.61 mm/sup 2/ achieves an open base collector-to-emitter blocking voltage (V/sub ceo/) of 1677 V and conducts up to 3.2 A at a forward voltage drop of V/sub CE/=3.0 V, corresponding to a low R/spl I.bar//sub ON/ of 5.7 m/spl Omega//spl middot/cm/sup 2/ up to Jc=525 A/cm/sup 2/ and a record high value of V/sub B//sup 2//R/sub SP/spl I.bar/ON/ of 493 MW/cm/sup 2/.     

4H-SiC power bipolar junction transistor with a very low specific ON-resistance of 2.9 m/spl Omega//spl middot/cm/sup 2/

This letter reports a newly achieved best result on the specific ON-resistance (R/sub SP/spl I.bar/ON/) of power 4H-SiC bipolar junction transistors (BJTs). A 4H-SiC BJT based on a 12-/spl mu/m drift layer shows a record-low specific-ON resistance of only 2.9 m/spl Omega//spl middot/cm/sup 2/, with an open-base collector-to-emitter blocking voltage (V/sub ceo/) of 757 V, and a current gain of 18.8. The active area of this 4H-SiC BJT is 0.61 mm/sup 2/, and it has a fully interdigitated design. This high-performance 4H-SiC BJT conducts up to 5.24 A at a forward voltage drop of V/sub CE/=2.5 V, corresponding to a low R/sub SP-ON/ of 2.9 m/spl Omega//spl middot/cm/sup 2/ up to J/sub c/=859 A/cm/sup 2/. This is the lowest specific ON-resistance ever reported for high-power 4H-SiC BJTs.     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.     

Demonstration of 1789 V, 6.68 m/spl Omega/ /spl middot/ cm/sup 2/ 4H-SiC merged-PiN-Schottky diodes

The design, fabrication and characterisation of a high performance 4H-SiC diode of 1789 V-6.6 A with a low differential specific-on resistance (R/sub SP/spl I.bar/ON/) of 6.68 m/spl Omega/ /spl middot/ cm/sup 2/, based on a 10.3 /spl mu/m 4H-SiC blocking layer doped to 6.6/spl times/10/sup 15/ cm/sup -3/, is reported. The corresponding figure-of-merit of V/sub B//sup 2//R/sub SP/spl I.bar/ON/ for this diode is 479 MW/cm/sup 2/, which substantially surpasses previous records for all other MPS diodes.     

A 4.15 kV 9.07-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC Schottky-barrier diode using Mo contact annealed at high temperature

In this letter, we report the fabrication of high-voltage and low-loss 4H-SiC Schottky-barrier diodes (SBDs) with a performance close to the theoretical limit using a Mo contact annealed at high-temperature. High-temperature annealing for the Mo contact was found to be effective in controlling the Schottky-barrier height at 1.2-1.3 eV without degradation of n-factor and reverse characteristics. We successfully obtained a 1-mm/sup 2/ Mo-4H-SiC SBD with a breakdown voltage (V/sub b/) of 4.15 kV and a specific on resistance (R/sub on/) of 9.07 m/spl Omega//spl middot/cm/sup 2/, achieving a best V/sub b//sup 2//R/sub on/ value of 1898 MW/cm/sup 2/. We also obtained a 9-mm/sup 2/ Mo-4H-SiC SBD with V/sub b/ of 4.40 kV and R/sub on/ of 12.20 m/spl Omega//spl middot/cm/sup 2/.     

A 183 GHz f/sub T/ and 165 GHz f/sub max/ regrown-emitter DHBT with abrupt InP emitter

Small-area regrown emitter-base junction InP/In-GaAs/InP double heterojunction bipolar transistors (DHBT) using an abrupt InP emitter are presented for the first time. In a device with emitter-base junction area of 0.7 /spl times/ 8 /spl mu/m/sup 2/, a maximum 183 GHz f/sub T/ and 165 GHz f/sub max/ are exhibited. To our knowledge, this is the highest reported bandwidth for a III-V bipolar transistor utilizing emitter regrowth. The emitter current density is 6/spl times/10/sup 5/ A/cm/sup 2/ at V/sub CE,sat/ = 1.5 V. The small-signal current gain h/sub 21/ = 17, while collector breakdown voltage is near 6 V for the 1500-/spl Aring/-thick collector. The emitter structure, created by nonselective molecular beam epitaxy regrowth, combines a small-area emitter-base junction and a larger-area extrinsic emitter contact, and is similar in structure to that of a SiGe HBT. The higher f/sub T/ and f/sub max/ compared to previously reported devices are achieved by simplified regrowth using an InP emitter and by improvements to the regrowth surface preparation process.     

A 160-GHz f/sub T/ and 140-GHz f/sub MAX/ submicrometer InP DHBT in MBE regrown-emitter technology

We report a 0.7/spl times/8 /spl mu/m/sup 2/ InAlAs-InGaAs-InP double heterojunction bipolar transistor, fabricated in a molecular-beam epitaxy (MBE) regrown-emitter technology, exhibiting 160 GHz f/sub T/ and 140 GHz f/sub MAX/. These initial results are the first known RF results for a nonselective regrown-emitter heterojunction bipolar transistor, and the fastest ever reported using a regrown base-emitter heterojunction. The maximum current density is J/sub E/=8/spl times/10/sup 5/ A/cm/sup 2/ and the collector breakdown voltage V/sub CEO/ is 6 V for a 1500-/spl Aring/ collector. In this technology, the dimension of base-emitter junction has been scaled to an area as low as 0.3/spl times/4 /spl mu/m/sup 2/ while a larger-area extrinsic emitter maintains lower emitter access resistance. Furthermore, the application of a refractory metal (Ti-W) base contact beneath the extrinsic emitter regrowth achieves a fully self-aligned device topology.     

InGaAs-InP mesa DHBTs with simultaneously high f/sub /spl tau// and f/sub max/ and low C/sub cb//I/sub c/ ratio

We report an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT), fabricated using a conventional triple mesa structure, exhibiting a 370-GHz f/sub /spl tau// and 459-GHz f/sub max/, which is to our knowledge the highest f/sub /spl tau// reported for a mesa InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The collector semiconductor was undercut to reduce the base-collector capacitance, producing a C/sub cb//I/sub c/ ratio of 0.28 ps/V at V/sub cb/=0.5 V. The V/sub BR,CEO/ is 5.6 V and the devices fail thermally only at >18 mW//spl mu/m/sup 2/, allowing dc bias from J/sub e/=4.8 mA//spl mu/m/sup 2/ at V/sub ce/=3.9 V to J/sub e/=12.5 mA//spl mu/m/sup 2/ at V/sub ce/=1.5 V. The device employs a 30 nm carbon-doped InGaAs base with graded base doping, and an InGaAs-InAlAs superlattice grade in the base-collector junction that contributes to a total depleted collector thickness of 150 nm.     

High-responsivity high-gain In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors grown using metal-organic vapor phase epitaxy

We report the growth and fabrication of bound-to-bound In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors using metal-organic vapor phase epitaxy. These detectors have a peak detection wavelength of 8.5 /spl mu/m. The peak responsivities are extremely large with R/sub pk/=6.9 A/W at bias voltage V/sub b/=3.4 V and temperature T=10 K. These large responsivities arise from large detector gain that was found to be g/sub n/=82 at V/sub b/=3.8 V from dark current noise measurements at T=77 K and g/sub p/=18.4 at V/sub b/=3.4 V from photoresponse data at T=10 K. The background-limited temperature with F/1.2 optics is T/sub BLIP/=65 K for 0相似文献   

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ 4H-SiC power DMOSFETs

10-kV, 123-m/spl Omega//spl middot/cm/sup 2/ power DMOSFETs in 4H-SiC are demonstrated. A 42% reduction in R/sub on,sp/, compared to a previously reported value, was achieved by using an 8 /spl times/ 10/sup 14/ cm/sup -3/ doped, 85-/spl mu/m-thick drift epilayer. An effective channel mobility of 22 cm/sup 2//Vs was measured from a test MOSFET. A specific on-resistance of 123 m/spl Omega//spl middot/cm/sup 2/ were measured with a gate bias of 18 V, which corresponds to an E/sub ox/ of 3 MV/cm. A leakage current of 197 /spl mu/A was measured at a drain bias of 10 kV from a 4H-SiC DMOSFET with an active area of 4.24 /spl times/ 10/sup -3/ cm/sup 2/. A switching time of 100 ns was measured in 4.6-kV, 1.3-A switching measurements. This shows that the 4H-SiC power DMOSFETS are ideal for high-voltage, high-speed switching applications.     

1330 V, 67 m/spl Omega//spl middot/cm/sup 2/ 4H-SiC(0001) RESURF MOSFET

Design and fabrication of 4H-SiC(0001) lateral MOSFETs with a two-zone reduced surface field structure have been investigated. The dose dependencies of experimental breakdown voltage show good agreement with simulation. Through the optimization of implant dose, high-temperature (1700/spl deg/C) annealing after ion implantation, and reduction of channel length, a breakdown voltage of 1330 V and a low on-resistance of 67 m/spl Omega//spl middot/cm/sup 2/ have been obtained. The figure-of-merit (V/sub B//sup 2//R/sub on/) of the present device reaches 26 MW/cm/sup 2/, being the best performance among lateral MOSFETs reported. The temperature dependence of static characteristics is also presented.     

GaInP/GaAs collector-up tunneling-collector heterojunction bipolar transistors (C-up TC-HBTs): optimization of fabrication process and epitaxial layer structure for high-efficiency high-power amplifiers

This paper describes a novel heterojunction bipolar transistor (HBT) structure, the collector-up tunneling-collector HBT (C-up TC-HBT), that minimizes the offset voltage V/sub CE,sat/ and the knee voltage V/sub k/. In this device, a thin GaInP layer is used as a tunnel barrier at the base-collector (BC) junction to suppress hole injection into the collector, which results in small V/sub CE,sat/. Collector-up configuration is used because of the observed asymmetry of the band discontinuity between GaInP and GaAs depending on growth direction. To minimize V/sub k/, we optimized the epitaxial layer structure as well as the conditions of ion implantation into the extrinsic emitter and post-implantation annealing. The best results were obtained when a 5-nm-thick 5/spl times/10/sup 17/-cm/sup -3/-doped GaInP tunnel barrier with a 20-nm-thick undoped GaAs spacer was used at the BC junction, and when 2/spl times/10/sup 12/-cm/sup -2/ 50-keV B implantation was employed followed by 10-min annealing at 390/spl deg/C. Fabricated 40/spl times/40-/spl mu/m/sup 2/ C-up TC-HBTs showed almost zero V/sub CE,sat/ (<10 mV) and a very small V/sub k/ of 0.29 V at a collector current density of 4 kA/cm/sub 2/, which are much lower than those of a typical GaInP/GaAs HBT. The results indicate that the C-up TC-HBT's are attractive candidates for high-efficiency high power amplifiers.     

InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.     

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The authors demonstrate high-performing n-channel transistors with a HfO/sub 2//TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 /spl Aring/, a leakage current of 1.5 A/cm/sup 2/ at V/sub G/=1 V, a peak mobility of 190 cm/sup 2//V/spl middot/s, and a drive-current of 815 /spl mu/A//spl mu/m at an off-state current of 0.1 /spl mu/A//spl mu/m for V/sub DD/=1.2 V. Identical gate stacks processed with a 1000-/spl deg/C spike anneal have a higher peak mobility at 275 cm/sup 2//V/spl middot/s, but a 5-/spl Aring/ higher EOT and a reduced drive current at 610 /spl mu/A//spl mu/m. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 /spl deg/C) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.     

Lateral RESURF MOSFET fabricated on 4H-SiC(0001/sup ~/) C-face

Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature.     

Evidence and understanding of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors outperforming sandwich counterparts

Metal-insulator-metal capacitors with atomic-layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminated and sandwiched dielectrics have been compared, for the first time, for analog circuit applications. The experimental results indicate that significant improvements can be obtained using the laminated dielectrics, including an extremely low leakage current of 1/spl times/10/sup -9/ A/cm/sup 2/ at 3.3V and 125/spl deg/C, a high breakdown electric field of /spl sim/3.3MV/cm at 125/spl deg/C, good polarity-independent electrical characteristics, while retaining relatively high capacitance density of 3.13 fF//spl mu/m/sup 2/ as well as voltage coefficients of capacitance as low as -80 ppm/V and 100 ppm/V/sup 2/ at 100 kHz. The underlying mechanism is likely due to alternate insertions of Al/sub 2/O/sub 3/ layers that reduce the thickness of each HfO/sub 2/ layer, hereby efficiently inhibiting HfO/sub 2/ crystallization, and blocking extensions of grain boundary channels from top to bottom as well as to achieve good interfacial quality.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.