Machine learning-based novelty detection for faulty wafer detection in semiconductor manufacturing

Since semiconductor manufacturing consists of hundreds of processes, a faulty wafer detection system, which allows for earlier detection of faulty wafers, is required. statistical process control (SPC) and virtual metrology (VM) have been used to detect faulty wafers. However, there are some limitations in that SPC requires linear, unimodal and single variable data and VM underestimates the deviations of predictors. In this paper, seven different machine learning-based novelty detection methods were employed to detect faulty wafers. The models were trained with Fault Detection and Classification (FDC) data to detect wafers having faulty metrology values. The real world semiconductor manufacturing data collected from a semiconductor fab were tested. Since the real world data have more than 150 input variables, we employed three different dimensionality reduction methods. The experimental results showed a high True Positive Rate (TPR). These results are promising enough to warrant further study.     

Optimizing class-constrained wafer-to-order allocation in semiconductor back-end production

This paper studies the problem of allocating semiconductor wafers to customer orders with the objective of minimizing the overallocation prior to assembly. It is an important problem for back-end semiconductor manufacturing as overallocation may have severe impact on operational performance due to excess inventory and unnecessarily occupied manufacturing equipment. In practice, a wafer can contain dies from several different die classes, making the wafer-allocation problem more challenging. As a novel contribution of this work, we explicitly consider the existence of multiple die classes on a wafer in the wafer-allocation problem. An integer linear programming formulation of the class-constrained wafer allocation problem is provided. The formulation is further extended to be more flexible by allowing the dies from different classes on the same wafer to be allocated to distinct customer orders. A real-world case study from the back-end assembly and test facility of a semiconductor manufacturer is presented. Experiments with real-world data show that the proposed method significantly reduces the overallocation performance in current practice and allows planners to quantify the value of flexibility in wafer allocation.     

基于局部与非局部线性判别分析和高斯混合模型动态集成的晶圆表面缺陷探测与识别

在复杂的半导体制造过程中,晶圆生产经过薄膜沉积、蚀刻、抛光等多项复杂的工序,制造过程中的异常波动都可能导致晶圆缺陷产生.晶圆表面的缺陷模式通常反映了半导体制造过程的各种异常问题,生产线上通过探测和识别晶圆表面缺陷,可及时判断制造过程故障源并进行在线调整,降低晶圆成品率损失.本文提出了基于一种流形学习算法与高斯混合模型动态集成的晶圆表面缺陷在线探测与识别模型.首先该模型开发了一种新型流形学习算法——局部与非局部线性判别分析法(Local and nonlocal linear discriminant analysis, LNLDA),通过融合数据局部/非局部信息以及局部/非局部惩罚信息,有效地提取高维晶圆特征数据的内在流形结构信息,以最大化数据不同簇样本的低维映射距离,保持特征数据中相同簇的低维几何结构.针对线上晶圆缺陷产生的随机性和复杂性,该模型对每种晶圆缺陷模式构建相应的高斯混合模型(Gaussian mixture model, GMM),提出了基于高斯混合模型动态集成的晶圆缺陷在线探测与识别方法.本文提出的模型成功地应用到实际半导体制造过程的晶圆表面缺陷在线探测与识别,在WM-811K晶圆数据库的实验结果验证了该模型的有效性与实用性.     

Wafer defect inspection by neural analysis of region features

Wafer defect inspection is an important process that is performed before die packaging. Conventional wafer inspections are usually performed using human visual judgment. A large number of people visually inspect wafers and hand-mark the defective regions. This requires considerable personnel resources and misjudgment may be introduced due to human fatigue. In order to overcome these shortcomings, this study develops an automatic inspection system that can recognize defective LED dies. An artificial neural network is adopted in the inspection. Actual data obtained from a semiconductor manufacturing company in Taiwan were used in the experiments. The results show that the proposed approach successfully identified the defective dies on LED wafers. Personnel costs and misjudgment due to human fatigue can be reduced using the proposed approach.     

Evaluating the 300 mm wafer-handling task in semiconductor industry

The semiconductor industry is moving from the production of 200 mm wafers to 300 mm wafers. With the increase in wafer size, the workload of wafer handling tasks is also increasing. This study evaluated the operator's handling capability, and the risk of having musculoskeletal disorders (MSDs) for handling 300 mm wafers. Twenty-four female operators from a semiconductor manufacturing company participated in the experiment. Subject’s psychophysical, and physiological responses were measured. Posture analysis and biomechanics analysis were also conducted to evaluate the local strain at different joints. The results suggest that loading and unloading front opening universal pod (FOUP) at 90/90 cm is best for enhancing handling capability, wrist posture, and minimizing L5/S1 compression force. About 30% of the operator's FOUP handling capabilities were lower than the safe load limit (25%ile Maximal alleptable weight of lift) recommended by SEMI (Semiconductor Equipment and Materials International). Handling wafers at 90/125 tends to increase the risk of causing shoulder and wrist injuries. Handling wafers at 90/35 tends to induce greater strength loading at hip joint, and cause greater wrist radial deviation. To minimize the risk of having MSDs, countermeasures such as training appropriate method of FOUP handling, minimizing manual carrying, specifying ergonomic machine equipment interface, and assigning male operators for high frequency FOUP handling tasks were proposed. Positive feedbacks are obtained.

Relevance to industry

The results of this study provided useful information to improve the design of 300 mm wafer handling task, which enhanced the safety and health of operators in the semiconductor manufacturing workplace.     

Evaluating the reliability level of virtual metrology results for flexible process control: a novelty detection-based approach

The purpose of virtual metrology (VM) in semiconductor manufacturing is to support process monitoring and quality control by predicting the metrological values of every wafer without an actual metrology process, based on process sensor data collected during the operation. Most VM-based quality control schemes assume that the VM predictions are always accurate, which in fact may not be true due to some unexpected variations that can occur during the process. In this paper, therefore, we propose a means of evaluating the reliability level of VM prediction results based on novelty detection techniques, which would allow flexible utilization of the VM results. Our models generate a high-reliability score for a wafer’s VM prediction only when its process sensor values are found to be consistent with those of the majority of wafers that are used in model building; otherwise, a low-reliability score is returned. Thus, process engineers can selectively utilize VM results based on their reliability level. Experimental results show that our reliability generation models are effective; the VM results for wafers with a high level of reliability were found to be much more accurate than those with a low level.     

Causal modelling of semiconductor fabrication

Semiconductor fabrication is the manufacturing process by which wafers of silicon are turned into integrated circuits. Reasoning about how wafers are affected by fabrication operations is an important aspect in getting computers to aid in the diagnosis of manufacturing faults and in the design of new fabrication processes. Our research has been aimed at characterizing the knowledge needed to construct qualitative, causal models that can support diagnosis and design of the processes by which semiconductors are manufactured. This article presents our models of wafer structure and the operations that are used in semiconductor fabrication, and describes how a domain-independent simulator uses these models to determine how the operations affect the wafer structure. We also demonstrate how the causal dependencies recorded by the simulator can be used to diagnose manufacturing faults. We conclude with a comparison of our method of using discrete, causal models to other methods of modelling semiconductor fabrication.     

传感器网络中健壮数据聚集算法

节约能量以提高网络寿命是传感器网络研究面临的重要挑战.网内聚集查询在中间节点对数据进行预处理,可以减少消息传送的数量或者大小,从而实现能量的有效利用,但是,目前的聚集查询研究假设采样数据都是正确的.而目前的异常检测算法以检测率作为首要目标,不考虑能量的消耗,也不考虑查询的特点.所以将两方面的研究成果简单地结合在一起并不能产生很好的效果.分析了错误和异常数据可能对聚集结果造成的影响,提出了健壮聚集算法RAA(robust aggregation algorithm).RAA 对传统聚集查询进行了改进,在聚集的同时利用读向量相似性判断数据是否发生了错误或异常,删除错误数据,聚集正常数据并报告异常,使用户可以对网络目前状况有清晰的理解.最后,比较了RAA 和TAGVoting(在使用TAG(tiny aggregation)算法聚集的同时利用Voting算法进行异常检测),实验结果表明,RAA 算法在能量消耗和异常检测率方面都优于TAGVoting.     

Hierarchical indices to detect equipment condition changes with high dimensional data for semiconductor manufacturing

During semiconductor manufacturing process, massive and various types of interrelated equipment data are automatically collected for fault detection and classification. Indeed, unusual wafer measurements may reflect a wafer defect or a change in equipment conditions. Early detection of equipment condition changes assists the engineer with efficient maintenance. This study aims to develop hierarchical indices for equipment monitoring. For efficiency, only the highest level index is used for real-time monitoring. Once the index decreases, the engineers can use the drilled down indices to identify potential root causes. For validation, the proposed approach was tested in a leading semiconductor foundry in Taiwan. The results have shown that the proposed approach and associated indices can detect equipment condition changes after preventive maintenance efficiently and effectively.     

A virtual metrology system for semiconductor manufacturing

Nowadays, the semiconductor manufacturing becomes very complex, consisting of hundreds of individual processes. If a faulty wafer is produced in an early stage but detected at the last moment, unnecessary resource consumption is unavoidable. Measuring every wafer’s quality after each process can save resources, but it is unrealistic and impractical because additional measuring processes put in between each pair of contiguous processes significantly increase the total production time. Metrology, as is employed for product quality monitoring tool today, covers only a small fraction of sampled wafers. Virtual metrology (VM), on the other hand, enables to predict every wafer’s metrology measurements based on production equipment data and preceding metrology results. A well established VM system, therefore, can help improve product quality and reduce production cost and cycle time. In this paper, we develop a VM system for an etching process in semiconductor manufacturing based on various data mining techniques. The experimental results show that our VM system can not only predict the metrology measurement accurately, but also detect possible faulty wafers with a reasonable confidence.     

深度自编码器在数据异常检测中的应用研究

针对自编码器网络（AE）需要正常数据进行训练的局限性,结合主成分分析方法,将AE的每次重建输出与输入数据进行求差,隔离出异常数据部分,即将输入数据分为正常与异常部分,正常部分由AE重建输出,异常部分由近端法进行优化输出,最后采用交替方向乘子法训练整个模型并达到预定训练次数再输出结果,实现了一种基于深度自编码网络（DAE）模型的无监督数据异常检测方法。在7个真实数据集与8种机器学习模型和AE模型进行了对比实验,结果表明,DAE模型无需输入正常数据就可以有效进行模型训练,且可以防止模型的过拟合,其综合表现高于传统机器学习模型和AE模型,AUC值在4个数据集中达到最优。在mnist数据集中,DAE模型的AUC值相比于孤立森林（IF）方法提高了10.93%。     

A new intelligent SOFM-based sampling plan for advanced process control

Sample measurement inspecting for a process parameter is a necessity in semiconductor manufacturing because of the prohibitive amount of time involved in 100% inspection while maintaining sensitivity to all types of defects and abnormality. In current industrial practice, sample measurement locations are chosen approximately evenly across the wafer, in order to have all regions of the wafer equally well represented, but they are not adequate if process-related defective chips are distributed with spatial pattern within the wafer.In this paper, we propose the methodology for generating effective measurement sampling plan for process parameter by applying the Self-Organizing Feature Map (SOFM) network, unsupervised learning neural network, to wafer bin map data within a certain time period. The sampling plan specifies which chips within the wafer need to be inspected, and how many chips within the wafer need to be inspected for a good sensitivity of 100% wafer coverage and defect detection. We finally illustrate the effectiveness of our proposed sampling plan using actual semiconductor fab data.     

晶圆表面缺陷模式的在线探测与自适应识别研究

晶圆表面的缺陷通常反映了半导体制造过程存在的异常问题,通过探测与识别晶圆表面缺陷模式,可及时诊断故障源并进行在线调整。提出了一种晶圆表面缺陷模式的在线探测与自适应识别模型。首先该模型对晶圆表面的缺陷模式进行特征提取,基于特征集对每种晶圆模式构建相应的隐马尔科夫模型（Hidden Markov Model,HMM）,并提出基于HMM动态集成的晶圆缺陷在线探测与识别方法。提出的模型成功应用于WM-811K数据库的晶圆缺陷检测与识别中,实验结果充分证明了该模型的有效性与实用性。     

Integrated maintenance and operations decision making with imperfect degradation state observations

In highly flexible and integrated manufacturing systems, such as semiconductor fabs, strong interactions between the equipment condition, operations executed on the various machines and the outgoing product quality necessitate integrated decision making in the domains of maintenance scheduling and production operations. Furthermore, in highly complex manufacturing equipment, the underlying condition is not directly observable and can only be inferred probabilistically from the available sensor readings. In order to deal with interactions between maintenance and production operations in Flexible Manufacturing Systems (FMSs) in which equipment conditions are not perfectly observable, we propose in this paper a decision-making method based on a Partially Observable Markov Decision Processes (POMDP's), yielding an integrated policy in the realms of maintenance scheduling and production sequencing. Optimization was pursued using a metaheuristic method that used the results of discrete-event simulations of the underlying manufacturing system. The new approach is demonstrated in simulations of a generic semiconductor manufacturing cluster tool. The results showed that, regardless of uncertainties in the knowledge of actual equipment conditions, jointly making maintenance and production sequencing decisions consistently outperforms the current practice of making these decisions separately.     

一种电力感知数据的离群点检测方案

鉴于离群点引发的数据质量问题给电力应用造成的不良影响,对电力感知数据的特征进行了分析,并基于电力感知数据的时间特征和异常检测技术的易用性需求,提出一种电力感知数据的离群点检测方案。该方案由异常检测服务框架和离群点检测方法构成。异常检测服务框架借鉴Web服务的思想,基于大数据技术,能够支持电力感知数据的存储和计算,并且以服务的形式提供电力感知数据的异常检测能力。离群点检测方法是基于聚类算法和考虑时间属性的数据分段方法来检测电力感知数据中的离群点异常。通过实验验证了该方法的可行性和有效性,结果表明该方法能够有效识别具有时间相关性和连续性的电力感知数据中存在的离群点,且在数据规模增大时,具有良好的并行性和可扩展性。     

Defect spatial pattern recognition using a hybrid SOM–SVM approach in semiconductor manufacturing

As manufacturing geometries continue to shrink and circuit performance increases, fast fault detection and semiconductor yield improvement is of increasing concern. Circuits must be controlled to reduce parametric yield loss, and the resulting circuits tested to guarantee that they meet specifications. In this paper, a hybrid approach that integrates the Self-Organizing Map and Support Vector Machine for wafer bin map classification is proposed. The log odds ratio test is employed as a spatial clustering measurement preprocessor to distinguish between the systematic and random wafer bin map distribution. After the smoothing step is performed on the wafer bin map, features such as co-occurrence matrix and moment invariants are extracted. The wafer bin maps are then clustered with the Self-Organizing Map using the aforementioned features. The Support Vector Machine is then applied to classify the wafer bin maps to identify the manufacturing defects. The proposed method can transform a large number of wafer bin maps into a small group of specific failure patterns and thus shorten the time and scope for troubleshooting to yield improvement. Real data on over 3000 wafers were applied to the proposed approach. The experimental results show that our approach can obtain over 90% classification accuracy and outperform back-propagation neural network.     

Defect cluster recognition system for fabricated semiconductor wafers

The International Technology Roadmap for Semiconductors (ITRS) identifies production test data as an essential element in improving design and technology in the manufacturing process feedback loop. One of the observations made from the high-volume production test data is that dies that fail due to a systematic failure have a tendency to form certain unique patterns that manifest as defect clusters at the wafer level. Identifying and categorising such clusters is a crucial step towards manufacturing yield improvement and implementation of real-time statistical process control. Addressing the semiconductor industry’s needs, this research proposes an automatic defect cluster recognition system for semiconductor wafers that achieves up to 95% accuracy (depending on the product type).     

An unsupervised neural network approach for automatic semiconductor wafer defect inspection

Semiconductor wafer defect inspection is an important process before die packaging. The defective regions are usually identified through visual judgment with the aid of a scanning electron microscope. Dozens of people visually check wafers and hand-mark their defective regions. Consequently, potential misjudgment may be introduced due to human fatigue. In addition, the process can incur significant personnel costs. Prior work has proposed automated visual wafer defect inspection that is based on supervised neural networks. Since it requires learned patterns specific to each application, its disadvantage is the lack of product flexibility. Self-organizing neural networks (SONNs) have been proven to have the capabilities of unsupervised auto-clustering. In this paper, an automatic wafer inspection system based on a self-organizing neural network is proposed. Based on real-world data, experimental results show, with good performance, that the proposed method successfully identifies the defective regions on wafers.     

Functional testing and characterisation of (bio-)chemical sensors on wafer level

An automated computer-assisted system for the functional testing and characterisation of (bio-)chemical sensors on wafer level is developed and integrated into a commercial prober station. The system enables the identification and selection of “good” sensors on wafer level and thus, allows to avoid further expensive bonding, encapsulation and packaging processes for defective or non-functioning sensor structures. Moreover, a specifically designed flow-through electrochemical microcell offers the possibility of wafer-level characterisation of (bio-)chemical sensors in terms of sensitivity, drift, hysteresis and response time at an early process stage. The system has been exemplarily tested using wafers combining pH-sensitive capacitive electrolyte-insulator-semiconductor structures as well as ion-sensitive field-effect transistors with different geometrical sizes and gate layouts.     

Optimal <Emphasis Type="Italic">K</Emphasis>-unit cycle scheduling of two-cluster tools with residency constraints and general robot moving times

The semiconductor manufacturing industry is significantly expensive both in equipment and materials. Cluster tools, a type of automated manufacturing system integrating processing modules and transport modules, are commonly used in this industry. Nowadays, multi-cluster tools, which are composed of several cluster tools connected by joint buffer modules, are often used for wafer production. This paper deals with K-unit cycle scheduling problems in single-armed two-cluster tools for processing identical wafers in deterministic settings. In a K-unit cycle, K wafers are exactly inserted into the two-cluster tool, and K completed wafers leave the two-cluster tool, usually not the same K wafers. Residency constraints and general moving times by the robot are both considered. The objective is to obtain optimal K-unit cycle schedules, which minimize cycle times. To analyze this scheduling problem in detail, a mixed integer linear programming (MILP) model is formulated and solved. Numerical examples are used to explain how the solution can be obtained from the MILP model in a K-unit cycle.