Fast implementations of generalized discrete time-frequencydistributions

Cohen's class of time-frequency distributions (TFDs) have significant potential for the analysis of complex signals. In order to evaluate the TFD of a signal using its samples, discrete-time TFDs (DTFDs) have been defined as the Fourier transform of a smoothed discrete autocorrelation. Existing algorithms evaluate real-valued DTFDs using FFTs of the conjugate-symmetric autocorrelation. Although the computation required to smooth the autocorrelation is often greater than that for the FFT, there are no widely applicable fast algorithms for this part of the processing. Since the FFT is relatively inexpensive, downsampling is ineffective for reducing computation. If the DTFD needs only to be evaluated at a few frequencies for each time instant, the cost per time-frequency sample can be extremely high. The authors introduce two approaches for reducing the computation time of DTFDs. First, they define approximations to real-valued DTFDs, using spectrograms, that admit fast, space-saving evaluations. Frequency downsampling reduces the computation time of these approximations. Next, they define DTFDs that admit fast evaluations over sparse sets of time-frequency samples. A single short time Fourier transform is calculated in order for DTPD time-frequency samples to be evaluated at an additional, fixed cost per sample     

Fast time-invariant implementations of Gaussian signal detectors

A new implementation is presented for the optimum likelihood ratio detector for stationary Gaussian signals in white Gaussian noise that uses only two causal time-invariant filters. This solution also has the advantage that fast algorithms based on the Levinson and Chandrasekhar equations can he used for the determination of these time-invariant filters. By using a notion of "closeness to stationarity,' there is a natural extension of the above results for nonstationary signal processes.     

Fast implementations of algebraic methods for three-dimensionalreconstruction from cone-beam data

The prime motivation of this work is to devise techniques that make the algebraic reconstruction technique (ART) and related methods more efficient for routine clinical use, while not compromising their accuracy. Since most of the computational effort of ART is spent for projection/backprojection operations, we first seek to optimize the projection algorithm. Existing projection algorithms are surveyed and it is found that these algorithms either lack accuracy or speed, or are not suitable for cone-beam reconstruction. We hence devise a new and more accurate extension to the splatting algorithm, a well-known voxel-driven projection method. We also describe a new three-dimensional (3-D) ray-driven projector that is considerably faster than the voxel-driven projector and, at the same time, more accurate and perfectly suited for the demands of cone beam. We then devise caching schemes for both ART and simultaneous ART (SART), which minimize the number of redundant computations for projection and backprojection and, at the same time, are very memory conscious. We find that with caching, the cost for an ART projection/backprojection operation can be reduced to the equivalent cost of 1.12 projections. We also find that SART, due to its image-based volume correction scheme, is considerably harder to accelerate with caching. Implementations of the algorithms yield run-time ratios TSART/TART between 1.5 and 1.15, depending on the amount of caching used.     

Graphene nanoribbon crossbar architecture for low power and dense circuit implementations

Crossbar array is a promising nanoscale architecture which can be used for logic circuit implementation. In this work, a graphene nanoribbon (GNR) based crossbar architecture is proposed. This design uses parallel GNRs as device channel and metal as gate, source and drain contacts. Schottky-barrier type graphene nanoribbon field-effect transistors (SB-GNRFETs) are formed at the cross points of the GNRs and the metallic gates. Benchmark circuits are implemented using the proposed crossbar, Si-CMOS and multi-gate Si-CMOS approaches to evaluate the performance of the crossbar architecture compared to the conventional CMOS logic design. The compact SPICE model of SB-GNRFET was used to simulate crossbar-based circuits. The CMOS circuits are also simulated using 16 nm technology parameters. Simulation results of benchmark circuits using SIS synthesis tool indicate that the GNR-based crossbar circuits outperform conventional CMOS circuits in low power applications. Area optimized cell libraries are implemented based on the asymmetric crossbar architecture. The area of the circuit can be more reduced using this architecture at the expense of higher delay. The crossbar cells can be combined with CMOS cells to exhibit better performance in terms of EDP.     

Fast execution for circuit consistency verification

In this paper, a fast solution for circuit consistency verification is investigated. It is an efficient algorithm that is implemented to compare the extracted layout data with the originally designed data. A special partitioning method is guided by the circuit philosophy. This method has two major features over other techniques. First, the average time complexity for verification is only O(M log M), where M is the size of the circuit. Second, it can not only detect the exact error point but also report simultaneously the corresponding correction in the interactive environment. These features will clearly make the design and verification tasks quicker and easier. Experimental results of this verification system show that the circuit comparison can be accomplished by the proposed circuit-based algorithm with nearly linear runtime complexity.     

非线性电子电路方程解的一种快速收敛算法

本文以非线性电子电路的支路特性为基础,从电子元件的工作点出发,导出求解非线性电子电路方程的快速收敛算法,较好的解决非线性电子电路方程在求解过程中出现的振荡现象和假收敛问题.     

Fast circuit switching for the next generation of high performancenetworks

Dynamic synchronous transfer mode (DTM) is a broadband network architecture based on fast circuit-switching augmented with dynamic reallocation of resources. It provides a service based on multicast, multirate channels with short setup delay and supports applications with real-time requirements on quality of service as well as applications with bursty, asynchronous traffic. The paper describes the DTM architecture and its distributed resource management scheme. Performance analysis results from network simulations are presented. The analysis is performed with respect to throughput and access delay for two network topologies: a dual bus and a grid of dual buses. The effects of varying user requirements, internode distances and transfer size are studied for uniform traffic patterns. The results indicate that the overhead for establishing channels is low (a few hundred microseconds), which gives a high degree of utilization even for short transfers. The analysis also shows that when channels are established very frequently, the signaling capacity limits the performance     

Fast full-wave analysis of planar microstrip circuit elements instratified media

The fast Hankel transform (FHT) algorithm is implemented in the mixed-potential integral-equation (MPIE) analysis of planar microstrip circuits in stratified media. The spatial-domain Green's functions are accurately and quickly obtained by applying the FHT algorithm to the exact spectral-domain counterparts. Therefore, the entire analysis procedure has high accuracy and efficiency. A nonuniform partition scheme is used to effectively model the rapid change of current distributions around discontinuities. A generalized supplementary equation accounting for arbitrary termination conditions at both feeding and load ends is also derived. The proposed method is used to design a single-stub band-stop filter and a compensated dc block circuit. Experimental measurements are performed to validate the computation     

Fast method for calculation of characteristic parameters of ionospheric radio circuit

A fast method for the determination of the arrival angles and the group delay associated with a given transmitter/receiver circuit at a fixed frequency is presented. The electronic density profile used (MQP) is given, as well as the method and equations utilised for the determination of the propagation characteristics.<>     

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.     

Fast acquisition clock and data recovery circuit with low jitter

This paper presents a half-rate clock and data recovery circuit (CDR)that combines the fast acquisition of a phase selection (PS) delay-locked loop (DLL) with the low jitter of a phase-locked loop (PLL). The PLL acquisition time improves considerably with use of a phase frequency magnitude detector(PFMD) that feeds back an estimate of the magnitude of the frequency difference in addition to the sign. Measurements in 0.5/spl mu/m CMOS technology show operation up to 700 Mb/s, a 7% acquisition range, an initial acquisition time of 8 bit times with jitter of 30% bit time, and jitter of 16 ps after the PLL acquires lock. With a phase frequency detector (PFD), the PLL locks in about 700 ns from an initial frequency difference of 7%. Measurements using a PFMD show the 700 ns PLL acquisition time is reduced on average by about a factor of 5 to 140 ns from an initial 7% frequency difference. The power dissipation is 300mW.     

Optoelectronic implementations of neural networks

The ability of optical systems to provide the massive interconnections between processors required in most neural network models, which constitutes their chief advantage for such applications, is discussed, focusing on holography. Because of the essential nonlinearity of the holographic connections, nonlinear processing elements are needed to perform complex computations. The use of GaAs hybrid optoelectronic processing elements is examined. GaAs is an excellent material for this purpose, since it can be used to fabricate both fast electronic circuits and optical sources and detectors. It is shown how a complete hybrid neural computer can be implemented using available technology developed for conventional computing. An experimentally demonstrated network in which optics plays an even larger role is described     

Fast binary logarithm computing circuit for binary numbers less than one

A fast and expandable circuit for computing the approximate binary logarithm and antilogarithm of a fractional binary number is described. Illustration examples are included, and accuracy of the circuit is discussed.     

Fast, quasi-3D modeling of base resistance for circuit simulation

Modifications are made to a finite-difference device simulator (PISCES) to model distributed base resistance. The simulator is modified to run in a quasi-3-D mode in which two numerically simulated dimensions model the lateral flow of the base current, and the third dimension is modeled with the modified Gummel-Poon (MGP) equations. The modulation of the intrinsic base sheet resistivity and the base current injection at each node are determined by the MGP model. Basewidth modulation, high injection, emitter debiasing, bias dependence of current paths, and interactions among these effects are studied for a variety of drawn geometries, sheet resistances, and temperatures. It is found that the standard models used in circuit simulation (SPICE) do not adequately model some of these effects. A model that adds an extra term into the function of base resistance is introduced to model these effects. Performing curve fits to the simulation results allows the base resistance parameters to be expressed as a polynomial sum in terms of geometry, the intrinsic and extrinsic sheet resistivities, and temperature     

WCDMA系统中匹配滤波器的FPGA实现

WCDMA中规定了小区搜索的时隙同步过程采用匹配滤波器的方法实现,本论文主要研究匹配滤波器原理及FPGA实现结构。     

NCO的数字化实现及应用

NCO(数控振荡器)是数字信号处理中经常遇到的问题。概括介绍了基于FPGA的NCO数字化实现方法,并从原理上作了必要的分析,结合实际情况简要地分析了EDA软件中IP Core的缺陷及数字化实现的意义。     

VLSI implementations of communication protocols-a survey

Several protocol controllers for the IEEE 802 local area networks are surveyed and some characteristics for classifying them are given. Some case studies from these controllers are given as illustrations. Two new developments-the protocol engine and the programmable protocol engine-are also described. The protocol engine, currently under development, implements a new protocol called XTP which performs the functions of both the network and transport layers. The programmable protocol engine can implement several connection-oriented protocols by changing contents of a programmable random access memory     

DSP implementations of sophisticated speech codecs

Hardware implementation aspects of sophisticated speech codecs are addressed. The major points discussed are approaches to implementation of the sophisticated speech codecs, requirements for DSP (digital signal-processing) implementation of the codecs, such as the type of arithmetic processing and the necessity of bit-level specifications, and codec implementation and DSP programming techniques for three specific coding algorithms: 32-kb/s ADPCM (adaptive digital pulse code modulation), 64-kb/s (7 kHz) SB (subband)-ADPCM, and 16-kb/s APC-AB (adaptive predictive coding with adaptive but allocation) codecs     

Programmable implementations of xDSL transceiver systems

After a background on digital subscriber line (DSL) technology, this article evaluates the trade-offs between programmable and custom implementations of communications products with an emphasis on xDSL modems. These trade-offs include time to market, risk, flexibility, power consumption, and cost. A key issue is the processing power required to implement the modem. The article takes a detailed look at the processing power required to implement an ADSL or VDSL modem on a programmable platform. It is demonstrated that today's digital signal processors meet the processing power requirements for an ADSL modem, and it is estimated that the processing requirements of a VDSL modem will be met in the near future     

Performance comparison of different MSK implementations

Minimum-shift keying (MSK) can be implemented as binary continuous-phase frequency-shift keying (CPFSK) or a special form of offset quadrature phase-shift keying (OQPSK). A modified CPFSK implementation is proposed for AWGN channels since the conventional CPFSK implementation suffers from error propagation