An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation

In the era of digital signal processing, like graphics and computation systems, multiplication-accumulation is one of the prime operations. A MAC unit is a vital component of a digital system, like different Fast Fourier Transform (FFT) algorithms, convolution, image processing algorithms, etcetera. In the domain of digital signal processing, the use of normalization architecture is very vast. The main objective of using normalization is to perform comparison and shift operations. In this research paper, an evolutionary approach for designing an optimized normalization algorithm is proposed using basic logical blocks such as Multiplexer, Adder etc. The proposed normalization algorithm is further used in designing an 8 × 8 bit Signed Floating-Point Multiply-Accumulate (SFMAC) architecture. Since the SFMAC can accept an 8-bit significand and a 3-bit exponent, the input to thesaid architecture can be somewhere between −(7.96872)₁₀ to + (7.96872)₁₀. The proposed architecture is designed and implemented using the Cadence Virtuoso using 90 and 130 nm technologies (in Generic Process Design Kit (GPDK) and Taiwan Semiconductor Manufacturing Company (TSMC), respectively). To reduce the power consumption of the proposed normalization architecture, techniques such as “block enabling” and “clock gating” are used rigorously. According to the analysis done on Cadence, the proposed architecture uses the least amount of power compared to its current predecessors.     

An Optimized SW/HW AVMF Design Based on High-Level Synthesis Flow for Color Images

In this paper, a software/hardware High-level Synthesis (HLS) design is proposed to compute the Adaptive Vector Median Filter (AVMF) in real-time. In fact, this filter is known by its excellent impulsive noise suppression and chromaticity conservation. The software (SW) study of this filter demonstrates that its implementation is too complex. The purpose of this work is to study the impact of using an HLS tool to design ideal floating-point and optimized fixed-point hardware (HW) architectures for the AVMF filter using square root function (ideal HW) and ROM memory (optimized HW), respectively, to select the best HLS architectures and to design an efficient HLS software/hardware (SW/HW) embedded AVMF design to achieve a trade-off between the processing time, power consumption and hardware cost. For that purpose, some approximations using ROM memory were proposed to perform the square root and develop a fixed-point AVMF algorithm. After that, the best solution generated for each HLS design was integrated in the SW/HW environment and evaluated under ZC702 FPGA platform. The experimental results showed a reduction of about 65% and 98% in both the power consumption and processing time for the ideal SW/HW implementation relative to the ideal SW implementation for an AVMF filter with the same image quality, respectively. Moreover, the power consumption and processing time of the optimized SW/HW are 70% and 97% less than the optimized SW implementation, respectively. In addition, the Look Up Table (LUTs) percentage, power consumption and processing time used by the optimized SW/HW design are improved by nearly 45%, 18% and 61% compared the ideal SW/HW design, respectively, with slight decrease in the image quality.     

Grand alliance MPEG-2-based video decoder with parallel processing architecture

A practical and unique hardware architecture for video bitstream source decoding and video postprocessing of a Moving Pictures Expert Group (MPEG-2)-based high-definition television (HDTV) compressed bitstream has been implemented to impose minimal limitations on the video source coding algorithm. The Grand Alliance (GA) MPEG-2-based HDTV codec achieves a high degree of source and channel coding efficiency while preserving the delivery of high-resoultion picture quality in a variety of video input and output formats in bandwidth-limited channels. The video source decoder hardware architecture necessary to achieve the data decoding and ensuing video postprocessing poses numerous technologic challenges to the system designer, who must tradeoff minimizing codec constraints with the eventual commercialization of a video decoder for a consumer television receiver product. The powerful and flexible coding algorithm necessary to satisfy the HDTV picture quality and transmission channel bandwidth limitation requirements results in an encoder-output bitstream that necessitates high throughout decoding. Although the transmitted bitstream is of constant rate due to rate buffering, bistreams internal to the codec are both peaky and bursty. An intelligent distributive parallel processing decoding architecture has been developed to dynamically partition the MPEG-2 bitstream into a number of decodable subset bitstreams, while placing minimal constraints on the encoding algorithm. This architecture allows for high-speed, efficient decoding of the bitstream, and can be a prelude to the development of a cost-effective consumer product. Further architecture refinements can be explored, including implementation in VLSI.     

基于Zynq的实时视频图像角点检测系统

针对机器视觉测量应用中,待测关键点的自动识别与定位中的角点信息提取问题,以ZYNQ系列可拓展平台内部ARM+FPGA的异构架构为基础,采用软硬件协同设计方法,搭建了一套可进行实时视频图像角点检测的系统。利用Vivado HLS工具,将角点检测算法封装成可以部署到PL端的IP核,极大地缩短了开发周期;对系统中各个模块进行了合理的任务分配,使得系统拥有ARM的灵活性以及FPGA的并行处理能力,展现了并行异构架构的优势。该系统中图像算法IP核可以进行灵活的算法替换和更新,为基于机器视觉检测的小型化应用提供了重要参考。     

Area-Efficient Min-Sum Decoder Design for High-Rate Quasi-Cyclic Low-Density Parity-Check Codes in Magnetic Recording

We report a silicon area efficient method for designing a quasi-cyclic (QC) low-density parity-check (LDPC) code decoder. Our design method is geared to magnetic recording that demands high code rate and very high decoding throughput under stringent silicon cost constraints. The key to designing the decoder is to transform the conventional formulation of the min-sum decoding algorithm in such a way that we can readily develop a hardware architecture with several desirable features: 1) silicon area saving potential inherent in the min-sum algorithm for high-rate codes can be fully exploited; 2) the decoder circuit critical path may be greatly reduced; and 3) check node processing and variable node processing can operate concurrently. For the purpose of demonstration, we designed application-specific integrated circuit decoders for four rate-8/9 regular-(4, 36) QC-LDPC codes that contain 512-byte, 1024-byte, 2048-byte, and 4096-byte user data per codeword, respectively. Synthesis results show that our design method can meet the beyond-2 Gb/s throughput requirement in future magnetic recording at minimal silicon area cost.     

Utilization of HEVC ChaCha20-Based Selective Encryption for Secure Telehealth Video Conferencing

Coronavirus (COVID-19) is a contagious disease that causes exceptional effect on healthcare organizations worldwide with dangerous impact on medical services within the hospitals. Because of the fast spread of COVID-19, the healthcare facilities could be a big source of disease infection. So, healthcare video consultations should be used to decrease face-to-face communication between clinician and patients. Healthcare video consultations may be beneficial for some COVID-19 conditions and reduce the need for face-to-face contact with a potentially positive patient without symptoms. These conditions are like top clinicians who provide remote consultations to develop treatment methodology and follow-up remotely, patients who consult about COVID-19, and those who have mild symptoms suggestive of the COVID-19 virus. Video consultations are a supplement to, and not a substitute for, telephone consultations. It may also form part of a broader COVID-19 distance care strategy that contains computerized screening, separation of possibly infectious patients within medical services, and computerized video-intensive observing of their intensive care that helps reduce mixing. Nowadays, the spread of the COVID-19 virus helps to expand the use of video healthcare consultations because it helps to exchange experiences and remote medical consultations, save costs and health procedures used to cope with the pandemic of the COVID-19 virus, and monitor the progress of treatment plans, moment by moment from a distance with precision, clarity and ease. From this perspective, this paper introduces a high-efficiency video coding (HEVC) ChaCha20-based selective encryption (SE) scheme for secure healthcare video Consultations. The proposed HEVC ChaCha20-based SE scheme uses the ChaCha20 for encrypting the sign bits of the Discrete Cosine Transform (DCT) and Motion Vector Difference (MVD) in the HEVC entropy phase. The main achievement of HEVC ChaCha20-based SE scheme is encrypting the most sensitive video bits with keeping low delay time, fixed bit rate of the HEVC, and format compliance. Experimental tests guarantee that the proposed HEVC ChaCha20-based SE scheme can ensure the confidentiality of the healthcare video consultations which has become easy to transmit through the internet.     

Efficient Authentication Scheme for UAV-Assisted Mobile Edge Computing

Preserving privacy is imperative in the new unmanned aerial vehicle (UAV)-assisted mobile edge computing (MEC) architecture to ensure that sensitive information is protected and kept secure throughout the communication. Simultaneously, efficiency must be considered while developing such a privacy-preserving scheme because the devices involved in these architectures are resource constrained. This study proposes a lightweight and efficient authentication scheme for the UAV-assisted MEC environment. The proposed scheme is a hardware-based password-less authentication mechanism that is based on the fact that temporal and memory-related efficiency can be significantly improved while maintaining the data security by adopting a hardware-based solution with a simple implementation. The proposed scheme works in four stages: system initialization, EU registration, EU authentication, and session establishment. It is implemented as a single hardware chip comprising registers and XOR gates, and it can run the entire process in one clock cycle. Consequently, the proposed scheme has significantly higher efficiency in terms of runtime and memory consumption compared to other prevalent methods in the area. Simulations are conducted to evaluate the proposed authentication algorithm. The results show that the scheme has an average execution time of 0.986 ms and consumes average memory of 34 KB. The hardware execution time is approximately 0.39 ns, which is a significantly less than the prevalent schemes, whose execution times range in milliseconds. Furthermore, the security of the proposed scheme is examined, and it is resistant to brute-force attacks. Around 1.158 × 10⁷⁷ trials are required to overcome the system’s security, which is not feasible using fastest available processors.     

Hybrid Single Image Super-Resolution Algorithm for Medical Images

High-quality medical microscopic images used for diseases detection are expensive and difficult to store. Therefore, low-resolution images are favorable due to their low storage space and ease of sharing, where the images can be enlarged when needed using Super-Resolution (SR) techniques. However, it is important to maintain the shape and size of the medical images while enlarging them. One of the problems facing SR is that the performance of medical image diagnosis is very poor due to the deterioration of the reconstructed image resolution. Consequently, this paper suggests a multi-SR and classification framework based on Generative Adversarial Network (GAN) to generate high-resolution images with higher quality and finer details to reduce blurring. The proposed framework comprises five GAN models: Enhanced SR Generative Adversarial Networks (ESRGAN), Enhanced deep SR GAN (EDSRGAN), Sub-Pixel-GAN, SRGAN, and Efficient Wider Activation-B GAN (WDSR-b-GAN). To train the proposed models, we have employed images from the famous BreakHis dataset and enlarged them by 4× and 16× upscale factors with the ground truth of the size of 256 × 256 × 3. Moreover, several evaluation metrics like Peak Signal-to-Noise Ratio (PSNR), Mean Squared Error (MSE), Structural Similarity Index (SSIM), Multiscale Structural Similarity Index (MS-SSIM), and histogram are applied to make comprehensive and objective comparisons to determine the best methods in terms of efficiency, training time, and storage space. The obtained results reveal the superiority of the proposed models over traditional and benchmark models in terms of color and texture restoration and detection by achieving an accuracy of 99.7433%.     

Inkjet Printed Metamaterial Loaded Antenna for WLAN/WiMAX Applications

In this paper, the design and performance analysis of an Inkjet-printed metamaterial loaded monopole antenna is presented for wireless local area network (WLAN) and worldwide interoperability for microwave access (WiMAX) applications. The proposed metamaterial structure consists of two layers, one is rectangular tuning fork-shaped antenna, and another layer is an inkjet-printed metamaterial superstate. The metamaterial layer is designed using four split-ring resonators (SRR) with an H-shaped inner structure to achieve negative-index metamaterial properties. The metamaterial structure is fabricated on low-cost photo paper substrate material using a conductive ink-based inkjet printing technique, which achieved dual negative refractive index bands of 2.25–4.25 GHz and 4.3–4.6 GHz. The antenna is designed using a rectangular tuning fork structure to operate at WLAN and WiMAX bands. The antenna is printed on 30 × 39 × 1.27 mm3 Rogers RO3010 substrate, which shows wide impedance bandwidth of 0.75 GHz (2.2 to 2.95 GHz) with 2 dB realized gain at 2.4 GHz. After integrating metamaterial structure, the impedance bandwidth becomes 1.25 GHz (2.33 to 3.58 GHz) with 2.6 dB realized gain at 2.4 GHz. The antenna bandwidth and gain have been increased using developed quad SRR based metasurface by 500 MHz and 0.6 dBi respectively. Moreover, the proposed quad SRR loaded antenna can be used for 2.4 GHz WLAN bands and 2.5 GHz WiMAX applications. The contribution of this work is to develop a cost-effective inject printed metamaterial to enhance the impedance bandwidth and realized the gain of a WLAN/WiMAX antenna.     

Compact Interlaced Dual Circularly Polarized Sequentially Rotated Dielectric-Resonator Antenna Array

In this study, a compact 2 × 2 interlaced sequentially rotated dual-polarized dielectric-resonator antenna array is proposed for 5.8 GHz applications. The array is composed of a novel unit elements that are made of rectangular dielectric resonator (RDR) coupled to an eye slot for generating the orthogonal modes, and to acquire circular polarization (CP) radiation. For the purpose of miniaturization and achieving dual polarized resonance, the array is fed by two interlaced ports and each port excites two radiating elements. The first port feeds horizontal elements to obtain left hand circular polarization (LHCP). The second port feeds vertical elements to obtain right hand circular polarization (RHCP). A quarter-wave length transformer is employed to reduce the attenuation and consequently increase the array gain performance. The 35 × 35 mm² () gains were 8.4 and 8.2 dBi for port 1 and port 2, respectively, with port isolations of −33.51 dB. The design achieves a voltage standing-wave ratio (VSWR) < −10 dB and an axial ratio (AR) ˂ − 3 dB bandwidth of 2.48% (5.766 to 5.911 GHz) for LHCP at port 1 and a VSWR < −10 dB and AR ˂ −3 dB bandwidth of 2.28% (5.788 to 5.922 GHz) for RHCP at port 2. The findings of the proposed design validate its use for ISM band applications.     

Optimal weighed Holoentropy for video compression: an advanced HEVC

ABSTRACT

In recent times, the applications of multimedia are rising in a greedy mode and hence the amount of video transactions is also increasing exponentially. This has shouted great demands on effective models on video encoding and also for reducing the transmission channel congestion. This research work introduces a managing technique termed weighted encoding for High-Efficiency Video Coding (HEVC). HEVC, also termed as MPEG-H Part 2 and H.265 is a video compression standard that is widely utilized AVC (H.264 or MPEG-4 Part 10). When compared to AVC, HEVC grants double the ratio of data compression at a similar level of quality of the video or considerably enhanced video quality at a similar bit rate. This work intends to optimize the weight that adopted in HEVC for encoding. For this, this paper proposes a new Iterative based propagation update in the water wave Optimization Algorithm (IPU-WWO), which is the improved form of Water wave Optimization (WWO). The performance of proposed IPU-WWO is compared over other conventional methods like Artificial Bee Colony (ABC), Firefly (FF), Particle Swarm Optimization (PSO) and Genetic Algorithm (GA) with respect to Peak Signal to Noise Ratio (PSNR). By doing the encoding process, it minimizes the video size with perceptually better quality video or PSNR.     

An experimental digital VCR for consumer use

An experimental digital VCR (DVCR hereinafter) was developed. The DVCR has two new technologies for reduction of tape consumption. One is a bit rate reduction technology of a component video signal down to around 25 Mbps and the other is a high density recording technology. The bit rate reduction technology is based on an 8×8/2×4×8 two dimensional DCT (Discrete Cosine Transform) and a VLC (Variable Length Coding) that completes over 5 macro blocks. Editing, trick plays and invisible error concealments also have been realized by this bit rate reduction while keeping the playback picture quality very high. The high density recording technology is based on ME tape and an ATF (Automatic Track Finding) system. A track pitch of 10 μm and a bit length on tape of 0.25 μm have been realized. The possibility of a higher linear recording density has been confirmed through theoretical analysis, simulations and experiments     

A Compact Flexible Circularly Polarized Implantable Antenna forBiotelemetry Applications

With the help of in-body antennas, the wireless communication among the implantable medical devices (IMDs) and exterior monitoring equipment, the telemetry system has brought us many benefits. Thus, a very thin-profile circularly polarized (CP) in-body antenna, functioning in ISM band at 2.45 GHz, is proposed. A tapered coplanar waveguide (CPW) method is used to excite the antenna. The radiator contains a pentagonal shape with five horizontal slits inside to obtain a circular polarization behavior. A bendable Roger Duroid RT5880 material (ε_r = 2.2, tanδ = 0.0009) with a typical 0.25 mm-thickness is used as a substrate. The proposed antenna has a total volume of 21 × 13 × 0.25 mm³. The antenna covers up a bandwidth of 2.38 to 2.53 GHz (150 MHz) in vacuum, while in skin tissue it covers 1.56 to 2.72 GHz (1.16 GHz) and in the muscle tissue covers 2.16 to 3.17 GHz (1.01 GHz). GHz). The flexion analysis in the x and y axes was also performed in simulation as the proposed antenna works with a wider bandwidth in the skin and muscle tissue. The simulation and the curved antenna measurements turned out to be in good agreement. The impedance bandwidth of −10 dB and the axis ratio bandwidth of 3 dB (AR) are measured on the skin and imitative gel of the pig at 27.78% and 35.5%, 13.5% and 4.9%, respectively, at a frequency of 2.45 GHz. The simulations revealed that the specific absorption rate (SAR) in the skin is 0.634 and 0.914 W/kg in muscle on 1g-tissue. The recommended SAR values are below the limits set by the federal communications commission (FCC). Finally, the proposed low-profile implantable antenna has achieved very compact size, flexibility, lower SAR values, high gain, higher impedance and axis ratio bandwidths in the skin and muscle tissues of the human body. This antenna is smaller in size and a good applicant for application in medical implants.     

A HEVC Video Steganalysis Algorithm Based on PU Partition Modes

Steganalysis is a technique used for detecting the existence of secret information embedded into cover media such as images and videos. Currently, with the higher speed of the Internet, videos have become a kind of main methods for transferring information. The latest video coding standard High Efficiency Video Coding (HEVC) shows better coding performance compared with the H.264/AVC standard published in the previous time. Therefore, since the HEVC was published, HEVC videos have been widely used as carriers of hidden information.
In this paper, a steganalysis algorithm is proposed to detect the latest HEVC video steganography method which is based on the modification of Prediction Units (PU) partition modes. To detect the embedded data, All the PU partition modes are extracted from P pictures, and the probability of each PU partition mode in cover videos and stego videos is adopted as the classification feature. Furthermore, feature optimization is applied, that the 25-dimensional steganalysis feature has been reduced to the 3-dimensional feature. Then the Support Vector Machine (SVM) is used to identify stego videos. It is demonstrated in experimental results that the proposed steganalysis algorithm can effectively detect the stego videos, and much higher classification accuracy has been achieved compared with state-of-the-art work.     

Th-Shaped Tunable Multi-Band Antenna for Modern Wireless Applications

A compact, reconfigurable antenna supporting multiple wireless services with a minimum number of switches is found lacking in literature and the same became the focus and outcome of this work. It was achieved by designing a Th-Shaped frequency reconfigurable multi-band microstrip planar antenna, based on use of a single switch within the radiating structure of the antenna. Three frequency bands (i.e., 2007–2501 MHz, 3660–3983 MHz and 9341–1046 MHz) can be operated with the switch in the ON switch state. In the OFF state of the switch, the antenna operates within the 2577–3280 MHz and 9379–1033 MHz Bands. The proposed antenna shows an acceptable input impedance match with Voltage Standing Wave Ratio (VSWR) less than 1.2. The peak radiation efficiency of the antenna is 82%. A reasonable gain is obtained from 1.22 to 3.31 dB within the operating bands is achieved. The proposed antenna supports Universal Mobile Telecommunication System (UMTS)-1920 to 2170 MHz, Worldwide Interoperability and Microwave Access (WiMAX)/Wireless Broadband/(Long Term Evolution) LTE2500–2500 to 2690 MHz, Fifth Generation (5G)-2500/3500 MHz, Wireless Fidelity (Wi-Fi)/ Bluetooth-2400 to 2480 MHz, and Satellite communication applications in X-Band-8000 to 12000 MHz. The overall planar dimension of the proposed antenna is 40 × 20 mm². The antenna was designed, along with the parametric study, using Electromagnetic (EM) simulation tool. The antenna prototype is fabricated for experimental validation with the simulated results. The proposed antenna is low profile, tunable, lightweight, cheap to fabricate and highly efficient and hence is deemed suitable for use in modern wireless communication electronic devices.     

Suitability of VVC and HEVC for Video Telehealth Systems

Video compression in medical video streaming is one of the key technologies associated with mobile healthcare. Seamless delivery of medical video streams over a resource constrained network emphasizes the need of a video codec that requires minimum bitrates and maintains high perceptual quality. This paper presents a comparative study between High Efficiency Video Coding (HEVC) and its potential successor Versatile Video Coding (VVC) in the context of healthcare. A large-scale subjective experiment comprising of twenty-four non-expert participants is presented for eight different test conditions in Full High Definition (FHD) videos. The presented analysis highlights the impact of compression artefacts on the perceptual quality of HEVC and VVC processed videos. Our results and findings show that VVC clearly outperforms HEVC in terms of achieving higher compression, while maintaining high quality in FHD videos. VVC requires upto 40% less bitrate for encoding an FHD video at excellent perceptual quality. We have provided rate-quality curves for both encoders and a degree of overlap across both codecs in terms of perceptual quality. Overall, there is a 71% degree of overlap in terms of quality between VVC and HEVC compressed videos for eight different test conditions.     

可逆变长编码的解码器设计及VLSI实现

变长编码(VLCs,Variable Length Codes)因其高效的数据压缩能力被广泛地应用在多媒体压缩领域,但VLCs的自身性质使它对信道错误的恢复能力很弱。随着在不可靠信道,如无线信道和网络上进行视频传送需求的增加,视频通讯的错误控制和错误恢复技术变得越来越重要。可逆变长编码(RVLCs,Reversible Variable Length Codes),当遇到传输错误时,充分利用了可用的数据,错误恢复能力强于VLCs。许多视频标准,如ITU H．263 ,ISO MPEG-4已经采用了RVLCs。本文详细描述了RVLCs解码器的解码算法和解码器的体系结构设计,给出了一个基于MPEG-4 ASP@L5的解码器VLSI实现。结果表明,该实现完全适用于MPEG-4实时编解码系统。     

An FPGA-friendly CABAC-encoding architecture with dataflow modelling programming

Video compression standards play an important role in video encoding, transmitting and decoding. To exploit the similarities or commonality among standards, a Reconfigurable Video Coding framework is developed in MPEG by employing a dataflow modelling method to modulate the basic configuration components of encoders or decoders. However, the entropy coding for bitstream generating and parsing during the configuration process is very complex, especially when employing the Context Adaptive Based Arithmetic Coding (CABAC). This paper proposes an optimized ‘Producer–Consumer’ architecture for CABAC by dataflow modelling. To achieve high-throughput and low-resource consumption, the buffer accessing speed and buffer size in the architecture is analysed and refined. The proposed CABAC is implemented by dataflow language Cal and is synthesized to FPGA. Results show that it can process 3.5 bins/cycle with a 10-byte buffer consumption at a 120?MHz working frequency. It is sufficient for real-time encoding of H.265/HEVC at level 6.2 main tier.     

实时图像识别系统

基于图像目标识别的智能性及实时性要求，设计出了一种实时图像识别系统。图像目标识别算法由知识型图像分割、基于子波变换的旋转不变性参数提取和神经网络分类器三部分组成：硬件系统由主控计算机；Ｉｎｔｅｌ８０８６０芯片、图像输入输出与预处理模块三部分硬件系统的性能指标超过ＴＲＷ公司的ＭａｒｋⅢ，接近ＭａｒｋⅢ，接ＭａｒｋⅣ。采用此系统实现了对非均匀光照或复杂背景下目标的实时识别。     

FPGA Implementation of Deep Leaning Model for Video Analytics

In recent years, deep neural networks have become a fascinating and influential research subject, and they play a critical role in video processing and analytics. Since, video analytics are predominantly hardware centric, exploration of implementing the deep neural networks in the hardware needs its brighter light of research. However, the computational complexity and resource constraints of deep neural networks are increasing exponentially by time. Convolutional neural networks are one of the most popular deep learning architecture especially for image classification and video analytics. But these algorithms need an efficient implement strategy for incorporating more real time computations in terms of handling the videos in the hardware. Field programmable Gate arrays (FPGA) is thought to be more advantageous in implementing the convolutional neural networks when compared to Graphics Processing Unit (GPU) in terms of energy efficient and low computational complexity. But still, an intelligent architecture is required for implementing the CNN in FPGA for processing the videos. This paper introduces a modern high-performance, energy-efficient Bat Pruned Ensembled Convolutional networks (BPEC-CNN) for processing the video in the hardware. The system integrates the Bat Evolutionary Pruned layers for CNN and implements the new shared Distributed Filtering Structures (DFS) for handing the filter layers in CNN with pipelined data-path in FPGA. In addition, the proposed system adopts the hardware-software co-design methodology for an energy efficiency and less computational complexity. The extensive experimentations are carried out using CASIA video datasets with ARTIX-7 FPGA boards (number) and various algorithms centric parameters such as accuracy, sensitivity, specificity and architecture centric parameters such as the power, area and throughput are analyzed. These results are then compared with the existing pruned CNN architectures such as CNN-Prunner in which the proposed architecture has been shown 25% better performance than the existing architectures.