Lattice-Mismatched $hbox{In}_{0.4}hbox{Ga}_{0.6} hbox{As}$ Source/Drain Stressors With In Situ Doping for Strained $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel n-MOSFETs

We report the first demonstration of a strained $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ channel n-MOSFET featuring in situ doped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ source/drain (S/D) regions. The in situ silicondoped $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ S/D was formed by a recess etch and a selective epitaxy of $hbox{In}_{0.4}hbox{Ga}_{0.6}hbox{As}$ in the S/D by metal–organic chemical vapor deposition. A lattice mismatch of $sim$0.9% between $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ and $hbox{In}_{0.4} hbox{Ga}_{0.6}hbox{As}$ S/D gives rise to lateral tensile strain and vertical compressive strain in the $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ channel region. In addition, the in situ Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.      

Low-Voltage and High-Speed Operations of 30-nm-Gate Pseudomorphic $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}/hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$ HEMTs Under Cryogenic Conditions

In this letter, we fabricated 30-nm-gate pseudomorphic In_0.52 Al_0.48As/In_0.7Ga_0.3As HEMTs with multilayer cap structures to reduce source and drain parasitic resistances; we measured their dc and radio-frequency characteristics at 300, 77, and 16 K under various bias conditions. The maximum cutoff frequency fT was 498 GHz at 300 K and 577 GHz at 77 K. The maximum fT exceeded 600 GHz at 16 K. Even at a drain-source voltage V _ds of 0.4 V, we obtained an fT of 500 GHz at 16 K. This indicates that cryogenic HEMTs are favorable for low-voltage and high-speed operations. Furthermore, the present 30-nm-gate HEMTs at 300 K show almost the same fT values at the same dc-power dissipation as compared to 85-nm-gate InSb-channel HEMTs. The improvement of the maximum-oscillation-frequency f _max values was also observed at 77 and 16 K.     

Fabrication of Self-Aligned Enhancement-Mode $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs With $ hbox{TaN/HfO}_{2}hbox{/AlN}$ Gate Stack

In this letter, we report the fabrication and characterization of self-aligned inversion-type enhancement-mode In_0.53Ga_0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). The In_0.53Ga_0.47As surface was passivated by atomic layer deposition of a 2.5-nm-thick AIN interfacial layer. In_0.53Ga_0.47As MOS capacitors showed an excellent frequency dispersion behavior. A maximum drive current of 18.5 muA/mum was obtained at a gate overdrive of 2 V for a MOSFET device with a gate length of 20 mum. An I_on/_off ratio of 104, a positive threshold voltage of 0.15 V, and a subthreshold slope of ~165 mV/dec were extracted from the transfer characteristics. The interface-trap density is estimated to be ~7-8 times 10¹² cm^-2 ldr eV^-1 from the subthreshold characteristics of the MOSFET.     

Extraction of the Effective Mobility of $ hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs

The extraction of the effective mobility on $hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ metal–oxide–semiconductor field-effect transistors (MOSFETs) is studied and shown to be greater than 3600 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. The removal of $C_{rm it}$ response in the split $C$–$V$ measurement of these devices is crucial to the accurate analysis of these devices. Low-temperature split $C$–$V$ can be used to freeze out the $D_{rm it}$ response to the ac signal but maintain its effect on the free carrier density through the substrate potential. Simulations that match this low-temperature data can then be “warmed up” to room temperature and an accurate measure of $Q_{rm inv}$ is achieved. These results confirm the fundamental performance advantages of $hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ MOSFETs.      

$hbox{In}_{0.53}hbox{Ga}_{0.47}hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth

Abstract-We report Al₂O₃Zln_0.53Ga_0.47As MOSFETs having both self-aligned in situ Mo source/drain ohmic contacts and self-aligned InAs source/drain n⁺ regions formed by MBE regrowth. The device epitaxial dimensions are small, as is required for 22-nm gate length MOSFETs; a 5-nm In_0.53Ga_0.47As channel with an In_0.4sAl_0.52As back confinement layer and the n⁺⁺ source/drain junctions do not extend below the 5-nm channel. A device with 200-nm gate length showed I_D = 0.95 mA/mum current density at V_GS = 4.0 V and g_m = 0.45 mS/mum peak transconductance at V_DS = 2.0 V.     

Lateral and Vertical Scaling of $hbox{In}_{0.7} hbox{Ga}_{0.3}hbox{As}$ HEMTs for Post-Si-CMOS Logic Applications

In this paper, we have experimentally investigated the impact of lateral and vertical scaling of In_0.7Ga_0.3As high-electron-mobility transistors (HEMTs) onto their logic performance. We have found that reducing the In_0.52Al_0.48As insulator thickness results in much better electrostatic integrity and improved short-channel behavior down to a gate length of around 60 nm. Our nearly enhancement-mode 60-nm HEMTs feature V_T = -0.02 V, DIBL = 93 mV/V, S = 88 mV/V, and I_ON/I_OFF = 1.6 times10⁴, at V _DD = 0.5 V. We also estimate a gate delay of CV/I = 1.6 ps at V_DD = 0.5 V. We have benchmarked these devices against state-of-the-art Si CMOS. For the same leakage current, which includes the gate leakage current, the InGaAs HEMTs exhibit 1.2times more current drive (I_ON) than the state-of-the-art 65-nm low-power CMOS technology at V _DD = 0.5 V.     

Electrical Properties of $hbox{Ga}_{2}hbox{O}_{3}/ hbox{GaAs}$ Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs

Electrical properties of $hbox{Ga}_{2}hbox{O}_{3}/hbox{GaAs}$ interfaces with GdGaO cap dielectrics used in recent enhancement-mode GaAs-based NMOSFETs which perform in line with theoretical model predictions are presented. Capacitors with GdGaO thickness ranging from 3.0 to 18 nm ($hbox{0.9} leq hbox{EOT} leq hbox{3.9} hbox{nm}$) have been characterized by capacitance–voltage measurements. Midgap interface state density $D_{rm it}$, effective workfunction $phi_{m}$, fixed charge $Q_{f}$, dielectric constant $kappa$, and low field leakage current density are $hbox{2} times hbox{10}^{11} hbox{cm}^{-2} cdot hbox{eV}^{-1}$, 4.93 eV, $-hbox{8.9} times hbox{10}^{11} hbox{cm}^{-2}$, 19.5, and $hbox{10}^{-9}{-} hbox{10}^{-8} hbox{A/cm}^{2}$, respectively. The presence of interfacial Gd was confirmed to dramatically degrade electrical interface properties. The data illuminate the intimate interplay between heterostructure and interface engineering to achieve optimum MOSFET operation.      

A Monte Carlo Study of $hbox{Hg}_{0.7}hbox{Cd}_{0.3}hbox{Te}$ e-APD

A simple Monte Carlo model is developed for understanding the multiplication process in HgCdTe infrared avalanche photodiodes and the impact of physical and technological parameters. A good agreement is achieved between simulations and experimental measurements of gain and excess noise factor. In both cases, an exponential gain and extremely low noise—$F sim hbox{1}$ for multiplication gains up to 1000—were observed on 5.1-$muhbox{m}$ cutoff devices at 77 K, indicative of a single carrier impact ionization. A comparison study is presented to explain the effect of different combinations of scattering processes on the avalanche phenomenon in HgCdTe.      

Resistive Switching Properties of $hbox{Au}/ hbox{ZrO}_{2}/hbox{Ag}$ Structure for Low-Voltage Nonvolatile Memory Applications

The reliable resistive switching properties of $hbox{Au}/hbox{ZrO}_{2}/ hbox{Ag}$ structure fabricated with full room temperature process are demonstrated in this letter. The tested devices show low operation voltages ($≪hbox{1}$ V), high resistance ratio (about $hbox{10}^{4}$), fast switching speed (50 ns), and reliable data retention (ten years extrapolation at both RT and 85 $^{circ}hbox{C}$). Moreover, the benefits of high yield and multilevel storage possibility make them promising in the next generation nonvolatile memory applications.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

Comparative Study of the Low-Frequency-Noise Behaviors in a-IGZO Thin-Film Transistors With $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ Gate Dielectrics

A comparative study is made of the low-frequency noise (LFN) in amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) with $hbox{Al}_{2}hbox{O}_{3}$ and $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ gate dielectrics. The LFN is proportional to $hbox{1}/f^{gamma}$, with $gamma sim hbox{1}$ for both devices, but the normalized noise for the $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ device is two to three orders of magnitude lower than that for the $hbox{Al}_{2} hbox{O}_{3}$ device. The mobility fluctuation is the dominant LFN mechanism in both devices, but the noise from the source/drain contacts becomes comparable to the intrinsic channel noise as the gate overdrive voltage increases in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices. The $hbox{SiN}_{x}$ interfacial layer is considered to be very effective in reducing LFN by suppressing the remote phonon scattering from the $hbox{Al}_{2}hbox{O}_{3}$ dielectric. Hooge's parameter is extracted to $sim !!hbox{6.0} times hbox{10}^{-3}$ in $hbox{Al}_{2}hbox{O}_{3}/hbox{SiN}_{x}$ devices.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

First Insight Into the Lifetime Acceleration Model of High-$k$ $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ Stacks for Advanced DRAM Technology Nodes

Long-term reliability results over six orders of magnitude in time are presented showing that the voltage acceleration model for $hbox{ZrO}_{2}/hbox{SiO}_{2}/hbox{ZrO}_{2}$ exhibits an exponential dependence with voltage, down to 2 V. The voltage acceleration parameter $gamma$ is between 10 and 15 $hbox{V}^{-1}$, depending on the biasing polarity. Soft-breakdown behavior (SILC) is evident prior to the onset of hard breakdown as a result of barrier lowering or charge accumulation in the high- $k$ film. Under ac stress conditions, this SILC branch is lowered in magnitude, translating to a gain in lifetime to breakdown.      

0.8-V Supply Voltage Deep-Submicrometer Inversion-Mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFET

We report the experimental demonstration of deep-submicrometer inversion-mode $hbox{In}_{0.75}hbox{Ga}_{0.25}hbox{As}$ MOSFETs with ALD high- $k$ $hbox{Al}_{2}hbox{O}_{3}$ as gate dielectric. In this letter, n-channel MOSFETs with 100–200-nm-long gates have been fabricated. At a supply voltage of 0.8 V, the fabricated devices with 200–130-nm-long gates exhibit drain currents of 232–440 $muhbox{A}/muhbox{m}$ and transconductances of 538–705 $muhbox{S}/muhbox{m}$. The 100-nm device has a drain current of 801 $muhbox{A}/muhbox{m}$ and a transconductance of 940 $muhbox{S}/muhbox{m}$. However, the device cannot be pinched off due to severe short-channel effect. Important scaling metrics, such as on/off current ratio, subthreshold swing, and drain-induced barrier lowering, are presented, and their relations to the short-channel effect are discussed.      

A Two-Step-Recess Process Based on Atomic-Layer Etching for High-Performance $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}hbox{/}hbox{In}_{0.53} hbox{Ga}_{0.47}hbox{As}$ p-HEMTs

We investigated 60-nm In_0.52Al_0.48As/In_0.53Ga_0.47As pseudomorphic high-electron mobility transistors (p-HEMTs) fabricated by using a Ne-based atomic-layer-etching (ALET) technology. The ALET process produced a reproducible etch rate of 1.47 Aring/cycle for an InP etch stop layer, an excellent InP etch selectivity of 70 against an In_0.52Al_0.48As barrier layer, and an rms surface-roughness value of 1.37 Aring for the exposed In_0.52Al_0.48As barrier after removing the InP etch stop layer. The application of the ALET technology for the gate recess of 60-nm In_0.52Al_0.48As/In_0.53Ga_0.47As p-HEMTs produced improved device parameters, including transconductance (G_M), cutoff frequencies (f_T)> and electron saturation velocity (vsat) in the channel layer, which is mainly due to the high etch selectivity and low plasma-induced damage to the gate area. The 60-nm In_0.52Al_0.48As/In_0.53Ga_0.47As p-HEMTs fabricated by using the ALET technology exhibited G_M,_Max = 1-17 S/mm, f_T = 398 GHz, and v_sat = 2.5 X 10⁷ cm/s.     

Resistive-Switching Characteristics of $hbox{Al}/ hbox{Pr}_{0.7}hbox{Ca}_{0.3}hbox{MnO}_{3}$ for Nonvolatile Memory Applications

A systematic study on the switching mechanism of an $hbox{Al}/ hbox{Pr}_{0.7}hbox{Ca}_{0.3}hbox{MnO}_{3}$ (PCMO) device was performed. A polycrystalline PCMO film was deposited using a conventional sputtering method. A thin Al layer was introduced to induce a reaction with the PCMO, forming aluminum oxide $(hbox{AlO}_{x})$. Transmission electron microscopy analysis of the interface between Al and PCMO showed that resistive switching was governed by the formation and dissolution of $hbox{AlO}_{x}$. Some basic memory characteristics, such as good cycle endurance and data retention of up to $hbox{10}^{4}$ s at 125 $^{circ}hbox{C}$, were also obtained. It also showed excellent switching uniformity and high device yield.      

RF and Logic Performance Improvement of $ hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}/hbox{InAs}/hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ Composite-Channel HEMT Using Gate-Sinking Technology

Eighty-nanometer-gate In_0.7Ga_0.3As/InAs/In_0.7Ga_0.3As composite-channel high-electron mobility transistors (HEMTs), which are fabricated using platinum buried gate as the Schottky contact metal, were evaluated for RF and logic application. After gate sinking at 250degC for 3 min, the device exhibited a high g_m value of 1590 mS/mm at V_d = 0.5 V, the current-gain cutoff frequency f_T was increased from 390 to 494 GHz, and the gate-delay time was decreased from 0.83 to 0.78 ps at supply voltage of 0.6 V. This is the highest f_T achieved for 80-nm-gate-length HEMT devices. These superior performances are attributed to the reduction of distance between gate and channel and the reduction of parasitic gate capacitances during the gate-sinking process. Moreover, such superior performances were achieved through a very simple and straightforward fabrication process with optimal epistructure of the device.     

A Theoretical Comparison of the Breakdown Behavior of $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ and InP Near-Infrared Single-Photon Avalanche Photodiodes

We study the breakdown characteristics and timing statistics of InP and $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ single-photon avalanche photodiodes (SPADs) with avalanche widths ranging from 0.2 to 1.0 $mu{hbox {m}}$ at room temperature using a random ionization path-length model. Our results show that, for a given avalanche width, the breakdown probability of $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ SPADs increases faster with overbias than InP SPADs. When we compared their timing statistics, we observed that, for a given breakdown probability, InP requires a shorter time to reach breakdown and exhibits a smaller timing jitter than $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ . However, due to the lower dark count probability and faster rise in breakdown probability with overbias, $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ SPADs with $hbox{avalanche} hbox{widths}leq 0.5 mu{hbox {m}}$ are more suitable for single-photon detection at telecommunication wavelengths than InP SPADs. Moreover, we predict that, in InP SPADs with $hbox{avalanche} hbox{widths}leq 0.3 mu{hbox {m}}$ and $hbox{In}_{0.52}hbox{Al}_{0.48}hbox{As}$ SPADs with $hbox{avalanche} hbox{widths}leq 0.2 mu{hbox {m}}$, the dark count probability is higher than the photon count probability for all applied biases.