H.264解码在ADDSP-BF533上的实现和优化

首先介绍了H.264解码器结构和解码实现流程;然后重点阐述了H.264解码器在ADDSP-BF533上的实现和优化策略.实验结果表明,H.264解码器的实现方法和优化策略较为有效,能够满足DSP实时解码的需求.     

H.264解码器的设计与优化

介绍了一种H.264(JVT)解码器的软件设计及其优化方法。以H.264测试模型jm50c为参考重新设计H.264解码器，为解码器的设计及优化提供了一种方法。试验结果表明，本方法与jm50c相比，解码速度提高了10-25倍。     

H.264高清解码器帧率控制显示系统的SOC实现

H.264视频压缩技术是压缩比很高的技术,且在同等压缩比下有较高的质量,H.264解码器的应用也越来越广泛,而显示控制系统在H.264解码器中是一个关键单元,本文讨论在H.264解码器中通过应用程序设定帧率,从而控制解码器解码速度的显示控制系统。     

一种H.264/AVC反变换反量化IP核设计

提出了一种适用于H.264/AVC解码器功能完整的反变换反量化IP核的设计.设计中采用同一处理单元完成三种不同的反变换,反变换反量化的每个步骤采用独立的门控时钟控制,逻辑复用和门控时钟降低了功耗.实现结果表明本设计满足1080i高清码流的实时解码要求.     

基于H.264和双树小波的多描述视频编码

本文针对互联网和无线信道等不可靠网络的视频传输问题,提出一种基于H.264和双树小波变换的多描述视频编码解决方案.采用分层的多描述视频编码框架,实现H.264和双树小波编码的有机结合.基本层用H.264编码器对视频信号进行低码率编码后,复制到各个描述;增强层用三维双树小波变换对原视频和基本层重建视频的差值进行编码,将产生的四棵三维小波树经噪声整形后两两组合,编码送到不同描述.在解码端,若能够接收到两个描述,则通过中心解码器实现高质量的视频重建;若丢失一个描述,则通过边解码器解码仍可保证一定质量的视频重建.实验结果表明在相同码率下,本算法的视频中心解码和边解码质量优于现有的多描述视频编码算法.     

基于SoC平台设计的H.264/AVC CAVLC解码器

提出了一种基于SoC平台的CAVLC解码器.在尽量减少时钟消耗的前提下,此解码器可以解码每个变换块中变换系数的熵编码码流,并将结果按照块扫描顺序并行输出.通过在XILJNX的ISE6.0 FPGA开发软件下仿真及分析表明,在120MHz时钟时可以满足10 Mb/s码率下H.264标准中Level3.0的性能要求.     

AVS和H.264通用IDCT模块的建模与验证

H.264和AVS协议在算法上有一定的相似性,IDCT算法的特性说明它适合被用来硬件加速.使用ARM的ESL工具SoC Designer,对AVS和H.264的算法模块IDCT进行复用建模,设计出一个能同时解码AVS和H.264码流的通用解码器的验证模型.     

基于DXVA的多路H.264高清视频解码器的实现

设计了一种基于微软DXVA接口的H.264多路高清视频解码器。定义了代表解码器和GPU的数据结构,通过调用定义的解码函数接口,可使解码器用在各种视频播放器中。实验证明,所设计的解码器在进行多路高清解码时无论解码速度还是CPU的占用率都比传统的软件解码器有很大的性能提升。     

基于TMS320DM642的H.264解码器优化

通过分析H.264软件解码器的结构和复杂度,确定了解码器在优化过程中的重点和难点,并结合TMS320DM642DSP性能特点,详细讨论了在TMS320DM642DSP平台上H.264解码器所采用的优化方法。这些方法主要涉及提高程序代码的并行性和增强存储器访问的效率,重点是运动补偿、IDCT等关键模块的优化。通过实验结果表明,本解码器可以实现CIF格式视频流的实时解码。     

基于码头分组的H.264变长解码算法优化

H.264标准在编解码模块定义了一种基于内容的变长编码(CAVLC),对于实时处理来说,若该部分计算量过大,将影响整个系统的处理速度。对H.264熵解码模块进行了研究,在分析了CAVLC码表特征后,利用分组优化查表思想,提出了码头分组的快速变长熵解码方法。结果表明该方法使得H.264解码器在熵解码模块质量没有下降的情况下,速度提高了4倍以上。     

H.264/AVC基本档次编码器实现时域可伸缩编码的方法

提出一种在H.264/AVC基本档次编码器中实现时域可伸缩编码的方案,该方案通过H.264/AVC标准所提供的多参考帧和内存管理控制操作机制来实现。对于现有的H.264/AVC解码器,不需任何修改,即可直接解码由本方案生成的时域可伸缩码流。     

A Very High Throughput Deblocking Filter for H.264/AVC

This paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filtering order of six units is proposed according to the H.264/AVC standard. With a parallel filtering order (fully compliant with H.264/AVC) and a dedicated data arrangement in local memory banks, the proposed architecture can process filtering operations for one macroblock with less filtering cycles than previously proposed approaches. Whereas, filtering efficiency is improved due to a novel computation scheduling and a dedicated architecture composed of six filtering cores. It can be used either into the decoder or the encoder as a hardware accelerator for the processor or can be embedded into a full-hardware codec. This developed Intellectual Property block-based on the proposed architecture supports multiple and high definition processing flows in real time. While working at clock frequency of 150 MHz, synthesized under 65 nm low power and low voltage CMOS standard cell technology, it easily meets the throughput requirements for 4 k video at 30 fps of all the levels in H.264/AVC video coding standard and consumes 25.08 Kgates.     

A Cost-Shared Quantization Algorithm and Its Implementation for Multi-Standard Video Codecs

Due to the growing demand of digital convergence, there is a need to have a video encoder/decoder (codec) that is capable of supporting multiple video standards on a single platform. High Efficiency Video Coding (HEVC), successor to H.264/MPEG-4 AVC, is a new standard under development that aims to substantially improve coding efficiency compared to AVC High Profile. This paper presents an efficient architecture based on a resource sharing strategy that can perform the quantization operation of the emerging HEVC encoder and six other video encoders: H.264/AVC, AVS, VC-1, MPEG-2, MPEG-4, and Motion JPEG (MJPEG). Since HEVC is still in the drafting stage, the proposed architecture is designed in such a way that any final changes can be accommodated into the design. The proposed quantizer architecture is completely division-free, as the division operation is replaced by shift and addition operations for all the codecs. The design is implemented on an FPGA and later synthesized in CMOS 0.18 μm technology. While working at 190 MHz, the design can decode a 1080p HD video at up to 61 frames per second. The multi-codec architecture is also suitable for low-cost VLSI implementation.     

A Novel Cost-Effective and Programmable VLSI Architecture of CAVLC Decoder for H.264/AVC

This paper proposes a novel cost-effective and programmable architecture of CAVLC decoder for H.264/AVC, including decoders for Coeff_token, T1_sign, Level, Total_zeros and Run_before. To simplify the hardware architecture and provide programmability, we propose four new techniques: a new group-based VLD with efficient memory (NG–VLDEM) for Coeff_token decoder, a novel combined architecture (NCA) for level decoder, a new group-based VLD with memory access once (GMAO) for Total_zeros decoder and a new VLD architecture based on multiplexers instead of searching memory (MISM) for Run_before decoder. With the above four techniques, the proposed CAVLC decoder can decode every syntax element within one clock cycle. Synthesis result shows that the hardware cost is 3,310 gates with 0.18 μm CMOS technology at a clock constrain of 125 MHz. Therefore, the proposed design is satisfied for real-time applications, such as H.264/AVC HD1080i video decoding.

Hardware solution for implementing the entire inverse IDCTs in HEVC decoder

Video compression performance of High Efficiency Video Coding (HEVC) is about twice of H.264/AVC video compression standard. The improvement in coding efficiency in HEVC is achieved by considerable increase in the computational load compared to H.264/AVC which is substantially very computational intensive. One of the units in HEVC which has changed considerably compared to H.264/AVC is Integer Discrete Cosine Transform (IDCT) unit. IDCT in HEVC standard includes 32 × 32, 16 × 16, 8 × 8 and 4 × 4 transforms. In this paper, a hardware solution for implementing the entire inverse IDCTs in HEVC decoder is proposed. The proposed hardware has a resource-sharing pipelined architecture. As a result, the hardware resources and computation time for implementing inverse IDCTs in HEVC decoder are reduced. Synthesis results by using NanGate OpenPDK 45 nm library indicate that the proposed hardware can achieve 222 MHz clock rate and can achieve real-time decoding of 4096 × 3072 video sequences with 70 fps.     

A 0.7-V 1.8-mW H.264/AVC 720p Video Decoder

The H.264/AVC video coding standard can deliver high compression efficiency at a cost of increased complexity and power. The increasing popularity of video capture and playback on portable devices requires that the power of the video codec be kept to a minimum. This work implements several architecture optimizations such as increased parallelism, pipelining with FIFOs, multiple voltage/frequency domains, and custom voltage-scalable SRAMs that enable low voltage operation to reduce the power of a high-definition decoder. Dynamic voltage and frequency scaling can efficiently adapt to the varying workloads by leveraging the low voltage capabilities and domain partitioning of the decoder. An H.264/AVC Baseline Level 3.2 decoder ASIC was fabricated in 65-nm CMOS and verified. For high definition 720p video decoding at 30 frames per second (fps), it operates down to 0.7$~$ V with a measured power of 1.8 mW, which is significantly lower than previously published results. The highly scalable decoder is capable of operating down to 0.5 V for decoding QCIF at 15 fps with a measured power of 29 $mu$W.      

一种切分H．264视频序列的方案

系统地介绍了H.264/AVC视频序列的结构,针对采用大序列验证H.264解码器时往往出现的重复性验证的问题,提出了合理切分视频序列并分别验证各个子序列的方案.实现了验证H.264解码器的灵活性,提高了验证的效率.     

H.264/AVC解码中帧内预测的硬件实现

根据H．264／AVC的特点，设计出一种适合于帧内预测解码的硬件实现方式，并且引入了帧场自适应模式，有利于提高解码效率，并将该结构配合其他设计好的解码器模块，在FPGA上实现了标准清晰度的H．264视频的实时解码。     

H.264/AVC硬件解码器设计及其验证策略

提出了一种H.264/AVC硬件解码器的SOC/ASIC设计方案,并在实现电路的基础上,重点分析了基于文中的硬件设计方案的验证策略。该设计方案已经在基于FPGA的验证平台上通过功能原型验证,结果证明,这是一个完全可行的H.264/AVC硬件解码设计方案。     

高效的H．264指数哥伦布解码器设计

H．264视频压缩标准凭借高压缩比和较好的图像质量，已经作为一种新型的标准被广泛接受。由于H.264的解码复杂度很高，软件实现难以满足实时性的要求，所以需要采用硬件解码。本文提出了一种针对H．264视频编码标准的可变长指数哥伦布码解码的硬件设计结构，给出了一种系统解码时间消耗与系统资源占用较少的硬件设计方案，最后给出了设计最终的仿真以及后端设计的结果。