A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

A 2.7-V GSM RF transceiver IC

A 2.7-V RF transceiver IC is intended for small, low-cost global system for mobile communications (GSM) handsets. This chip includes a quadrature modulator (QMOD) and an offset phase locked loop (OPLL) in the transmit path and a dual IF receiver that consists of a low noise amplifier (LNA) with an active-bias circuit, two Gilbert-cell mixers, a programmable gain linear amplifier (PGA), and a quadrature demodulator (QDEM). The IC also contains frequency dividers with a very high frequency voltage controlled oscillator (VHF-VCO) to simplify the receiver design. The system evaluation results are the phase error of 2.7° r.m.s. and the noise transmitted in the GSM receiving band of -163 dBc/Hz for transmitters and the reference sensitivity of -105 dBm for receivers. Power-control functions are provided for independent transmit and receive operation. The IC is implemented by using bipolar technology with f_T=15 GHz, r'_bb=150 Ω, and 0.6-μm features     

A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator

This paper presents a fully integrated 0.18-/spl mu/m CMOS Bluetooth transceiver. The chip consumes 33 mA in receive mode and 25 mA in transmit mode from a 3-V system supply. The receiver uses a low-IF (3-MHz) architecture, and the transmitter uses a direct modulation with ROM-based Gaussian low-pass filter and I/Q direct digital frequency synthesizer for high level of integration and low power consumption. A new frequency shift keying demodulator based on a delay-locked loop with a digital frequency offset canceller is proposed. The demodulator operates without harmonic distortion, handles up to /spl plusmn/160-kHz frequency offset, and consumes only 2 mA from a 1.8-V supply. The receiver dynamic range is from -78 dBm to -16 dBm at 0.1% bit-error rate, and the transmitter delivers a maximum of 0 dBm with 20-dB digital power control capability.     

Low‐Power Direct Conversion Transceiver for 915 MHz Band IEEE 802.15.4b Standard Based on 0.18 μm CMOS Technology

This paper presents the experimental results of a low‐power low‐cost RF transceiver for the 915 MHz band IEEE 802.15.4b standard. Low power and low cost are achieved by optimizing the transceiver architecture and circuit design techniques. The proposed transceiver shares the analog baseband section for both receive and transmit modes to reduce the silicon area. The RF transceiver consumes 11.2 mA in receive mode and 22.5 mA in transmit mode under a supply voltage of 1.8 V, in which 5 mA of quadrature voltage controlled oscillator is included. The proposed transceiver is implemented in a 0.18 μm CMOS process and occupies 10 mm² of silicon area.     

A mixed-signal GFSK demodulator for Bluetooth

A discrete-time mixed-signal Gaussian frequency-shift keying demodulator designed for a low intermediate frequency Bluetooth receiver performs FSK demodulation. Employing passive sampling and time-domain differentiation techniques, the demodulator performs quadrature demodulation while tolerating up to 200-kHz frequency offset. A distributed array of interleaved sampling circuits and a low-voltage multiplier allow both low-voltage operation and low power dissipation. Fabricated in a CMOS 0.25-/spl mu/m technology, the demodulator only dissipates 6 mW from a 2-V power supply.     

A single-chip GaAs RF transceiver for 1.9-GHz digital mobilecommunication systems

A 1.9-GHz single-chip GaAs RF transceiver has been successfully developed using a planar self-aligned gate FET suitable for low-cost and high-volume production. This IC includes a negative voltage generator for 3-V single voltage operation and a control logic circuit to control transmit and receive functions, together with RF front-end analog circuits-a power amplifier, an SPDT switch, two attenuators for transmit and receive modes, and a low-noise amplifier. The IC can deliver 22-dBm output power at 30% efficiency with 3-V single power supply, The new negative voltage generator operates with charge time of less than 200 ns, producing a low level of spurious outputs below -70 dBc through the power amplifier. The generator also suppresses gate-bias voltage deviations to within 0.05 V even when gate current of -144 μA flows. The IC incorporates a new interface circuit between the logic circuit and the switch which enables it to handle power outputs over 24 dBm with only an operating voltage of 3 V. This transceiver will be expected to enable size reductions in telephones for 1.9-GHz digital mobile communication systems     

A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications

This paper describes a single-chip RF transceiver LSI for 2.4-GHz-band Gaussian frequency shift-keying applications, such as Bluetooth. This chip uses a 0.18-/spl mu/m bulk CMOS process for lower current consumption. The LSI consists of almost all the required RF and IF building blocks: a transmit/receive antenna switch, a power amplifier, a low noise amplifier, an image rejection mixer, channel-selection filters, a limiter, a received signal strength indicator, a frequency discriminator, a voltage controlled oscillator, and a phase-locked loop synthesizer. The bandpass filter for channel selection was difficult to achieve since it operates at a low supply voltage. However, because large interference is roughly rejected at the output of the image rejection mixer and a wide-input-range bandpass filter with an optimized input bias is realized, the transceiver can operate at a supply voltage of 1.8 V. In the IF section, we adopted a circuit design using the minimum number of passive elements, resistors and capacitors, for a lower chip area of 10.2 mm/sup 2/.     

A low-power high-performance SiGe BiCMOS 802.11a/b/g transceiver IC for cellular and bluetooth Co-existence applications

This paper describes a high-performance WLAN 802.11a/b/g radio transceiver, optimized for low-power in mobile applications, and for co-existence with cellular and Bluetooth systems in the same terminal. The direct-conversion transceiver architecture is optimized in each mode for low-power operation without compromising the challenging RF performance targets. A key transceiver requirement is a sensitivity of -77 dBm (at the LNA input) in 54 Mb/s OFDM mode while in the presence of a GSM1900 transmitter interferer. The receiver chain achieves an overall noise figure of 2.8/3.2 dB, consuming 168/185 mW at 2.8 V for the 2.4/5GHz bands, respectively. Signal loopback and transmit power detection techniques are used in conjunction with the baseband modem processor to calibrate the transmitter LO leakage and the transceiver I/Q imbalances. Fabricated in a 70 GHz f/sub T/ 0.25-/spl mu/m SiGe BiCMOS technology for system-in-package (SiP) use, the dual-band, tri-mode transceiver occupies only 4.6 mm/sup 2/.     

A polar modulator transmitter for GSM/EDGE

This 0.5-/spl mu/m SiGe BiCMOS polar modulator IC adds EDGE transmit capability to a GSM transceiver IC without any RF filters. Envelope information is extracted from the transmit IF and applied to the phase-modulated carrier in an RF variable gain amplifier which follows the integrated transmit VCO. The dual-band IC supports all four GSM bands. In EDGE mode, the IC produces more than 1 dBm of output power with more than 6 dB of margin to the transmit spectrum mask and less than 3% rms phase error. In GSM mode, more than 7 dBm of output power is produced with noise in the receive band less than -164 dBc/Hz.     

A dual-mode 802.11b/bluetooth radio in 0.35-/spl mu/m CMOS

A fully integrated dual-mode CMOS transceiver tuned to 2.4 GHz consumes 65 mA in receive mode and 78 mA in transmit mode from a 3-V supply. The radio includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), and power amplifier, and is intended for use in 802.11b and Bluetooth applications. The Bluetooth receiver uses a low-IF architecture for higher level of integration and lower power consumption, while the 802.11b receiver is direct conversion. The receiver achieves a typical sensitivity of -88 dBm at 11 Mb/s for 802.11b, and -83 dBm for Bluetooth mode. The receiver minimum IIP3 is -8 dBm. Both transmitters use a direct-conversion architecture, and deliver a nominal output power of 0 dBm, with a power range of 20 dB in 2-dB steps.     

A 3-V, 0.35-/spl mu/m CMOS Bluetooth receiver IC

A fully integrated CMOS low-IF Bluetooth receiver is presented. The receiver consists of a radio frequency (RF) front end, a phase-locked loop (PLL), an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, and a frequency offset cancellation circuit. The highlights of the receiver include a low-power active complex filter with a nonconventional tuning scheme and a high-performance mixed-mode GFSK demodulator. The chip was fabricated on a 6.25-mm/sup 2/ die using TSMC 0.35-/spl mu/m standard CMOS process. -82 dBm sensitivity at 1e-3 bit error rate, -10 dBm IIP3, and 15 dB noise figure were achieved in the measurements. The receiver active current is about 65 mA from a 3-V power supply.     

A 2.2-V operation, 2.4-GHz single-chip GaAs MMIC transceiver forwireless applications

A 2.2-V operation, single-chip GaAs MMIC transceiver has been successfully developed for 2.4-GHz-band wireless applications such as wireless local area network terminals. The chip is fabricated using a planar self-aligned gate field-effect transistor. To generate sufficient negative voltage for gate-biasing and to enhance switch power handling capability under a 2.2-V supply, a newly designed negative voltage generator with a voltage doubler (NVG-VD) and a switch control logic circuit are integrated on the chip, together with a power amplifier, a transmit/receive switch, and a low-noise amplifier. The NVG-VD is designed to produce both a 3.3-V positive step-up voltage and a -2.1-V negative voltage under 2.2 V in operation voltage. Biased with these outputs, the logic circuit accommodates high power outputs of over 25 dBm with a low operating voltage of 2.2 V in transmit mode, With a 2.45-GHz modulated signal based on IS-95 standards, a 21-dBm output power and a 33% efficiency are obtained at a ±1.25-MHz-offset adjacent channel power rejection of -45 dBc. In receive mode, a low-noise amplifier achieves a 1.8-dB noise figure and an 11-dB gain with a 3.0-mA current. This transceiver enables significant size and weight reductions in 2.4-GHz-band wireless application terminals     

A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.     

A 2.4-GHz CMOS transceiver for Bluetooth

A fully integrated CMOS transceiver tuned to 2.4 GHz consumes 46 mA in receive mode and 47 mA in transmit mode from a 2.7-V supply. It includes all the receive and transmit building blocks, such as frequency synthesizer, voltage-controlled oscillator (VCO), power amplifier, and demodulator. The receiver uses a low-IF architecture for higher level of integration and lower power consumption. It achieves a sensitivity of -82 dBm at 0.1% BER, and a third-order input intercept point (IIP3) of -7 dBm. The direct-conversion transmitter delivers a GFSK modulated spectrum at a nominal output power of 4 dBm. The on-chip voltage controlled oscillator has a close-in phase-noise of -120 dBc/Hz at 3-MHz offset     

A 5-GHz direct-conversion CMOS transceiver

A CMOS transceiver fully compliant with IEEE 802.11a in the unlicensed national information infrastructure (UNII) band (5.15-5.35 GHz) achieves a receiver sensitivity of -5 dBm for 64-QAM (quadrature amplitude modulation) with an error vector magnitude (EVM) of -29.3 dB. A single-sideband mixing technique for local-oscillator signal generation avoids frequency pulling. Realized in 0.18-/spl mu/m CMOS and operating from 1.8-V power supply, the design consumes 171 mW in receive mode and 135 mW in transmit mode while occupying less than 13 mm/sup 2/.     

A GFSK demodulator for low-IF Bluetooth receiver

An efficient mixed-mode Gaussian frequency-shift keying (GFSK) demodulator with a frequency offset cancellation circuit is presented. The structure is suitable for a low-IF Bluetooth receiver and can also be applied to other receivers involving continuous phase shift keying (CPSK) signals. The demodulator implementation is robust to tolerate process variations without requiring calibration. It can also track and cancel the time-varying local oscillator frequency offset between transmitter and receiver during the entire reception period. The chip was fabricated in CMOS 0.35-/spl mu/m digital process; it consumes 3 mA from a 3-V power supply and occupies 0.7 mm/sup 2/ of silicon area. A 16.2-dB input signal-to-noise ratio is obtained to achieve 0.1% bit-error rate as specified in Bluetooth specs. The co-channel interference rejection ratio is about 11 dB. Theoretical and experimental results are in good agreement.     

A Bluetooth radio in 0.18-/spl mu/m CMOS

This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.     

All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS

We present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process. The transceiver is architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrated with a digital baseband and application processor. The conventional RF frequency synthesizer architecture, based on the voltage-controlled oscillator and the phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter, respectively. The transmitter architecture takes advantage of the wideband frequency modulation capability of the all-digital phase-locked loop with built-in automatic compensation to ensure modulation accuracy. The receiver employs a discrete-time architecture in which the RF signal is directly sampled and processed using analog and digital signal processing techniques. The complete chip also integrates power management functions and a digital baseband processor. Application of the presented ideas has resulted in significant area and power savings while producing structures that are amenable to migration to more advanced deep-submicron processes, as they become available. The entire IC occupies 10 mm/sup 2/ and consumes 28 mA during transmit and 41 mA during receive at 1.5-V supply.     

A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.