The limit of dynamic voltage scaling and insomniac dynamic voltage scaling

Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum V/sub dd/. However, there is no fundamental reason why designs cannot operate over a much larger voltage range: from full V/sub dd/ to subthreshold voltages. This possibility raises the question of whether a larger voltage range improves the energy efficiency of DVS. First, from a theoretical point of view, we show that, for subthreshold supply voltages, leakage energy becomes dominant, making "just-in-time computation" energy-inefficient at extremely low voltages. Hence, we introduce the existence of a so-called "energy-optimal voltage" which is the voltage at which the application is executed with the highest possible energy efficiency and below which voltage scaling reduces energy efficiency. We derive an analytical model for the energy-optimal voltage and study its trends with technology scaling and different application loads. Second, we compare several different low-power approaches including MTCMOS, standard DVS, and the proposed Insomniac (extended DVS into subthreshold operation). A study of real applications on commercial processors shows that Insomniac provides the best energy efficiency. From these results, we conclude that extending the voltage range below V/sub dd//2 will improve the energy efficiency for many processor designs.     

High-throughput asynchronous datapath with software-controlled voltage scaling

Adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation. In this paper, we describe the development of a high-performance asynchronous micropipelined datapath that provides robust interfaces across voltage domains, performing appropriate voltage level conversions and operating between stages with fanout-of-four delays differing by almost two orders of magnitude. With software-specified throughput requirements, the power supply of the datapath is scaled from 2.5 V to 650 mV using an on-chip dc-dc conversion system. Because of the asynchronous design style, the processor operates continuously during the voltage scaling transitions.     

Dynamic voltage scaling for series hybrid amplifiers

We present an optimization of the voltage scaling algorithm in low power audio class-G amplifier for headphones application to allow longer playback time. The optimization approach minimizes the voltage difference between the internal audio amplifier power supply and its output signal over a large range of operating conditions. The modeling is based on a behavioral model enabling accurate and rapid evaluation of efficiency and audio quality with realistic input stimuli. The model validated in practice is used to optimize the voltage scaling using only few power supply levels. Thanks to a global search algorithm followed by a local one, the optimization gives the better parameters for voltage scaling algorithm while keeping a good audio quality. The proposed configuration increases the efficiency up to 48% at nominal operation.     

Supply and threshold voltage scaling for low power CMOS

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields     

A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling

A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process.     

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm², which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.     

Low-energy GALS NoC with FIFO—Monitoring dynamic voltage scaling

In this paper we propose two dynamic voltage scaling (DVS) policies for a GALS NoC, which is designed based on fully asynchronous switch architectures. The first one is a history-based DVS policy, which exploits the link utilization and adjusts the voltages of different parts of the router among a few voltage levels. The second one is a FIFO-adaptive DVS, which uses two FIFO threshold levels for decision making. It judiciously adjusts supply voltage of each switch among only three voltage levels. The introduced architecture is simulated in 90 nm CMOS technology with accurate Spice simulations. Experimental results show that the FIFO-adaptive DVS not only lowers the implementation cost, but also in a 86 % saturated network achieves 36 % energy-delay product (ED) saving compared to the DVS policy based on link utilization.     

CHISEL programming operation of scaled NOR flash EEPROMs-effect of voltage scaling, device scaling and technological parameters

The impact of programming biases, device scaling and variation of technological parameters on channel initiated secondary electron (CHISEL) programming performance of scaled NOR Flash electrically erasable programmable read-only memories (EEPROMs) is studied in detail. It is shown that CHISEL operation offers faster programming for all bias conditions and remains highly efficient at lower biases compared to conventional channel hot electron (CHE) operation. The physical mechanism responsible for this behavior is explained using full band Monte Carlo simulations. CHISEL programming efficiency is shown to degrade with device scaling, and various technological parameter optimization schemes required for its improvement are explored. The resulting increase in drain disturbs is also studied and the impact of technological parameter optimization on the programming performance versus drain disturb tradeoff is analyzed. It is shown that by judicious choice of technological parameters the advantage of CHISEL programming can be maintained for deeply scaled electrically erasable programmable read-only memory (EEPROM) cells.     

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays

Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra low-power-supply voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active-mode energy consumption. Temperature-adaptive dynamic supply voltage tuning (TA-DVS) technique is proposed in this paper to reduce the high-temperature energy consumption of ultra low-voltage subthreshold SRAM arrays. Results indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures. The impact of the temperature-adaptive dynamic supply voltage scaling technique on the data stability of the subthreshold SRAM bit-cells is presented. The effectiveness of the TA-DVS technique under process parameter and supply voltage variations is evaluated. An alternative technique based on temperature-adaptive reverse body bias (TA-RBB) to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption characteristics of the two temperature-adaptive voltage tuning techniques are compared.     

Dynamic voltage scaling based energy-minimized partial task offloading in fog networks

Wireless Networks - With the dynamic voltage scaling (DVS) technology, the terminal node (TN) can dynamically adjust its computational speed, thus providing a new way to save energy during task...     

Standby power reduction using dynamic voltage scaling and canary flip-flop structures

Lowering V/sub DD/ during standby mode reduces power by decreasing both voltage and current. Analysis of flip-flop structures shows how low the voltage can scale before destroying the state information. Measurements of a 0.13-/spl mu/m, dual-V/sub T/ test chip show that reducing V/sub DD/ to near the point where state is lost gives the best power savings. We show that "canary" flip-flops provide a mechanism for observing the proximity to failure for the flip-flops. The canary flip-flops enable closed-loop standby voltage scaling for achieving savings near the optimum. This approach potentially provides over 2/spl times/ higher savings than an optimal open-loop approach without loss of state.     

Sensor based adaptive voltage scaling on FPGAs: Calibration and parametrization

The impacts of aging and process variations on the performance of VLSI systems is increasing with each process generation. The conventional way to counteract them are extensive guard bands, which are calculated at system design time. Hence, they are necessarily worst case guard bands, i.e., most often too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement based adaptive voltage scaling (AVS). The performance measurement is typically determined by means of dedicated sensors or canary logic. The parametrization of such AVS systems relies on assumptions regarding the relative behavior of the sensor and the application logic. Most published approaches use manually gained empirical data for this purpose. However, an automatic calibration procedure is needed for the practical application of these approaches. We propose such an automated calibration procedure and evaluate it on multiple FPGAs to consider the effects of aging and process variation. Furthermore, we use two designs to cover leakage power and dynamic power dominated scenarios. We achieve average power savings of 67% for a leakage dominated design and 48% for a test case with dominant dynamic power. Furthermore, we investigate the limitations of AVS systems regarding their capability to counteract fast disturbances, e.g., voltage drop.     

A yield improvement technique in severe process,voltage, and temperature variations and extreme voltage scaling

Drastic yield reduction at sub/nearthreshold voltage domains, caused by the severe process, voltage, and temperature (PVT) variations in this region, is challenging characteristic of recent nanometre sensory chips. Using a variation sensitive and ultra-low-power design, this paper proposes a novel technique capable of sensing and responding to PVT variations by providing an appropriate forward body bias (FBB) so that the delay variations and timing yield of whole system as well as energy-delay product (EDP) are improved. Theoretical analysis for the error probability, confirmed by post-layout HSPICE simulations for an 8-bit Kogge–Stone adder and also two large Fast Fourier Transform (FFT) processors, shows considerable improvements in severe PVT variations and extreme voltage scaling. For this adder, for example, the proposed technique can reduce error rate from 50% to 1% at 0.4 V. In another implementation, in average ∼7× delay variation and ∼4× EDP improvement is gained after this technique is applied to an iterative 1024pt, radix 4, complex FFT while working in sub/nearthreshold voltage region of 0.3 V–0.6 V. Also, pipelined version of the FFT consumed only 412pJ/FFT at 0.4 V while processing 125 K FFT/sec.     

Constant voltage scaling of FETs for high frequency and high power applications

A constant voltage scaling scheme is examined for the enhancement of frequency and power performance of FETs. For low electric fields, this scheme is self-consistent within Shockley's formulation and improves the overall frequency and power performance figure of merit by a factor of κ⁶ with a κ times reduction in the device area. For high electric fields, the improvement is reduced to κ³ times due to the velocity saturation effect. Reduced breakdown voltage further limit the improvement.     

电压调节技术用于SoC低功耗设计

针对便携设备在SOC系统设计中的功耗问题，通过电压调节和电压控制的方法来达到降低功耗的目的。可以用两种方法来实现，一种是开环电压调节(动态)，另一种是闭环(自适应)电压控制的方法。     

Predicting CMOS speed with gate oxide and voltage scaling andinterconnect loading effects

Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. I_dsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted     

Optimizing energy efficiency of CNN-based object detection with dynamic voltage and frequency scaling

On the one hand,accelerating convolution neural networks(CNNs)on FPGAs requires ever increasing high energy efficiency in the edge computing paradigm.On the other hand,unlike normal digital algorithms,CNNs maintain their high robustness even with limited timing errors.By taking advantage of this unique feature,we propose to use dynamic voltage and frequency scaling(DVFS)to further optimize the energy efficiency for CNNs.First,we have developed a DVFS framework on FPGAs.Second,we apply the DVFS to SkyNet,a state-of-the-art neural network targeting on object detection.Third,we analyze the impact of DVFS on CNNs in terms of performance,power,energy efficiency and accuracy.Compared to the state-of-the-art,experimental results show that we have achieved 38%improvement in energy efficiency without any loss in accuracy.Results also show that we can achieve 47%improvement in energy efficiency if we allow 0.11%relaxation in accuracy.     

Experimental confirmation of an accurate CMOS gate delay model forgate oxide and voltage scaling

MOSFET's and CMOS ring oscillators with gate oxide thicknesses from 2.58 nm to 5.7 nm and effective channel lengths down to 0.21 μm have been studied at voltages from 1.5 V to 3.3 V. Physical and electrical measurement of gate oxide thicknesses are compared. Ring oscillators' load capacitance is characterized through dynamic current measurement. An accurate model of CMOS gate delay is compared with measurement data. It shows that the dependence of gate propagation delay on gate oxide, channel length, and voltage scaling can be predicted     

基于DVFS的移动通信终端省电方案

本文首先概述了TD-SCDMA终端的耗电特性,接着对动态电压与频率调节技术进行了分析,最后运用动态管理技术提出了一种基于动态电压与频率调节技术的终端省电方案,有效地延长了终端的工作时间.