Single-chip image sensors with a digital processor array

The architectures, implementation and applications of two smart sensors, LAPP and PASIC, are described. The basic idea of these two designs is to integrate an image sensor array with a digital processor array in a single chip. The integrated camera-and-processor eliminates the bottleneck of sequential image read-out that characterizes conventional systems. They provide fast, compact and economic solutions for tasks such as industrial inspection, optical character recognition and robot vision.     

通用处理器多核流水线自适应同步方法

在通用处理器上进行信号处理是软件无线电发展的方向之一,现有的共享存储并行编程（OpenMP）和直接线程并行法难以对信号处理进行并行加速。针对串行算法的并行化问题,引入多核流水线方法,对传统串行方法和多核流水线的实时性进行了分析对比。针对多核流水线的同步问题,研究了一种分布式的自适应线程同步方法。结合信号处理实例,对串行方法和多核流水线的实时性进行测试,结果表明多核流水线的吞吐率是串行方法的2.1倍,处理能力大大提高。     

Lossless compression of HDR color filter array image for the digital camera pipeline

This paper introduces a lossless color filter array (CFA) image compression scheme capable of handling high dynamic range (HDR) representation. The proposed pipeline consists of a series of pre-processing operations followed by a JPEG XR encoding module. A deinterleaving step separates the CFA image to sub-images of a single color channel, and each sub-image is processed by a proposed weighted template matching prediction. The utilized JPEG XR codec allows the compression of HDR data at low computational cost. Extensive experimentation is performed using sample test HDR images to validate performance and the proposed pipeline outperforms existing lossless CFA compression solutions in terms of compression efficiency.     

CMOS image sensor with mixed-signal processor array

We present a single-chip integration of a CMOS image sensor with an embedded flexible processing array and dedicated analog-to-digital converter. The processor array is designed to perform convolution and transformation algorithms with arbitrary kernels. It has been designed to carry out the multiplication of analog image data with given digital kernel coefficients and to add up the results. The processor array is an analog implementation of a highly parallel architecture which is scalable to any desired sensor resolution while preserving video-rate operation. A prototype implementation has been realized in a 0.6-/spl mu/m CMOS technology. Switched current technique has been applied to obtain compact and robust circuits. The prototype's sensor resolution is 64 /spl times/ 128 pixels. The processor array occupies a small chip area and consumes only a small percentage of the power (250 /spl mu/W) of the whole image sensor.     

An LSI adaptive array processor

Describes an LSI adaptive array processor (AAP) for two-dimensional data processings. The AAP contains a large number of one-bit processing elements (PEs) arranged in a square array. The large degree of parallelism and control registers in each PE allow for high speed and flexible operations. High transfer capability is also obtained by a simple inter-PE connection network with hierarchical bypasses. The high applicability to various data processings is indicated by a matrix multiplication example, utilizing an algorithm similar to a systolic one. An AAP LSI composed of 8/spl times/8 PEs with powerful functions has been implemented in a 96.0 mm/SUP 2/ chip by using 2 /spl mu/m Si-gate p-well CMOS technology. A high-speed cycle time of 55 ns, low power dissipation of 1.1 W, and high packing density of 1170 transistors/mm/SUP 2/ has been achieved by a skilful manual design. Though the LSI contains as many as 111900 transistors, the design effort has only required one man-year due to cellular array regularity. This LSI is expected to realize a high-performance AAP compactly.     

Mixed signal SIMD processor array vision chip for real-time image processing

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31 μm pitch. Each processor element includes 14 bits of digital memory in addition to seven analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1 μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18 μm CMOS technology.     

Real-time image template matching based on systolic array processor

An architecture based on a systolic array for real-time image template matching is presented. The architecture consists mainly of four elements: a digitizer, a two-dimensional systolic array combined with variable-length shift register arrays, an adder tree, and a comparator. All the elements form a four-stage pipeline. The image data enter the pipe sequentially in the same order as the TV raster scan. The matching computation is, however, performed in a parallel manner. The analyses on time complexity and hardware complexity have shown that real-time performance is achieved. The analyses have also shown that the processing speed is higher and the hardware is simpler when compared to the architecture presented by Chou and Chen.     

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0-μm CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment     

A general purpose differential digital modulator implementationincorporating a direct digital synthesis method

A highly versatile digital modulator that uses a direct digital synthesis method to perform signal modulation is described. In contrast to the customary methods of implementing I-Q modulation schemes utilizing in-phase and quadrature branches, this design approach is based on directly accessing many of the digitally stored carrier modulating symbols according to the information bearing input signals. Apart from the digital-to-analog converter, all the previous stages are digital. To demonstrate the concept, a differential 16-QAM modulator was implemented. The technique lends itself to VLSI implementation. It can be considered as a digital implementation of a digital modulator     

An optical processor for radio pulses from an antenna array

A coherent optical method of processing pulsed radio signals received by a planar antenna array is described. The output is the two-dimensional optical image of the brightness distribution of the radio sky. Experimental results for a 4 × 4 array are presented.     

双重功能图像水印算法

提出一种能同时实现内容认证和版权保护双重功能的图像水印算法.首先,对原始图像进行分块奇异值分解(SVD),计算所有子块最大奇异值的均值,通过比较各子块的最大奇异值与所有子块最大奇异值的均值间的数值关系产生鲁棒零水印序列.然后,对原始图像进行分块离散余弦变换(DCT).调整图像子块DCT高频系数的数值大小,建立同一子块两...     

基于浮点DSP的数字图像压缩方法研究

分析了浮点ＤＳＰ（ＴＭＳ３２０Ｃ３１）的硬件资源、指令系统的特点,给出了各种提高编码效率的方法,进而介绍了一种采用ＴＭＳ３２０Ｃ３１实现静态图像压缩的方法,并简述了基于ＤＳＰ的视频图像压缩系统的性能。     

An image compression method for spatial search

The maintenance of large raster images under spatial operations is still a major performance bottleneck. For reasons of storage space, images in a collection, such as satellite pictures in geographic information systems, are maintained in compressed form. Instead of performing a spatially selective operation on an image by first decompressing the compressed version, we propose to perform queries directly on the compressed version of the image. We suggest a compression technique that allows for the subsequent use of a spatial index structure to guide a spatial search. In response to a window query, our algorithm delivers a compressed partial image, or the exact uncompressed requested image region. In addition to the support of spatial queries on compressed continuous tone images, the new compression algorithm is even competitive in terms of the compression ratio that it achieves, compared to other standard lossless compression techniques.     

海洋合成孔径雷达图像的一种高效压缩方法

针对通用压缩算法未利用合成孔径雷达（SAR）图像特征的不足,提出一种基于概率分布的自适应海洋SAR图像压缩算法。利用海洋SAR图像的概率分布,根据目标的分布设计量化方案,使目标和背景得到不同程度的保留。利用场景的稀疏性,将阈值以上的像素映射到三元组,对其灰度和位置信息分别熵编码;利用剩余背景层灰度偏差较小的特点作位平面编码。实验结果表明,该算法能有效地压缩图像,同码率下峰值信噪比（PSNR）较JPEG2000高5dB～10dB。本文算法复杂度低,对比度保持好,适用于针对不同需求的海面舰船SAR图像压缩。     

An adaptive array processor with robustness and broad-band capabilities

A new type of receiving array which adaptively minimizes ouput noise power while simultaneously satisfying certain robustness and/or bandwidth criteria is considered. The resulting array gains are shown to be robust against direction uncertainty in the assumed look direction, against wavefront distortions and against array geometry errors. The robustness property is incorporated directly into the adaption algorithm via constraints. Extensive simulation has established very satisfactory performance of this new algorithm, both as a limited broad-band processor and as a robust narrow-band processor.     

景象匹配算法在数字信号处理器上的实时实现

在图像处理中,灰度相关匹配是一种应用广泛而有效的经典匹配定位算法,但样关匹配的计算量比较大,使得匹配速度很难满足实时的需要。文中给出了灰度相关匹配算法在数字信号处理器TMS320C6201上的一种快速实现方法。根据二维图像的存储特点,通过图像数据的展开优化了匹配计算的实现,在保证匹配精度的前提下减少了计算时间。     

VLSI processor for image processing

Toshiba's VLSI processor T9506 is suitable for image processing applications, such as medical diagnosis and remote sensing. It performs FFT, Affine transform, spatial filtering, and histogram operation very quickly with high precision. T9506 architecture and application examples are described in this paper.     

Performance analysis of reversible image compression techniques for high-resolution digital teleradiology

The performances of a number of block-based, reversible, compression algorithms suitable for compression of very-large-format images (4096x4096 pixels or more) are compared to that of a novel two-dimensional linear predictive coder developed by extending the multichannel version of the Burg algorithm to two dimensions. The compression schemes implemented are: Huffman coding, Lempel-Ziv coding, arithmetic coding, two-dimensional linear predictive coding (in addition to the aforementioned one), transform coding using discrete Fourier-, discrete cosine-, and discrete Walsh transforms, linear interpolative coding, and combinations thereof. The performances of these coding techniques for a few mammograms and chest radiographs digitized to sizes up to 4096x4096 10 b pixels are discussed. Compression from 10 b to 2.5-3.0 b/pixel on these images has been achieved without any loss of information. The modified multichannel linear predictor outperforms the other methods while offering certain advantages in implementation.