Broad-band MMICs based on modified loss-compensation method using 0.35-/spl mu/m SiGe BiCMOS technology

Using the concept of loss compensation, novel broad-band monolithic microwave integrated circuits (MMICs), including an amplifier and an analog multiplier/mixer, with LC ladder matching networks in a commercial 0.35-mum SiGe BiCMOS technology are demonstrated for the first time. An HBT two-stage cascade single-stage distributed amplifier (2-CSSDA) using the modified loss-compensation technique is presented. It demonstrates a small-signal gain of better than 15 dB from dc to 28 GHz (gain-bandwidth product=157 GHz) with a low power consumption of 48 mW and a miniature chip size of 0.63 mm² including testing pads. The gain-bandwidth product of the modified loss-compensated CSSDA is improved approximately 68% compared with the conventional attenuation-compensation technique. The wide-band amplifier achieves a high gain-bandwidth product with the lowest power consumption and smallest chip size. The broad-band mixer designed using a Gilbert cell with the modified loss-compensation technique achieves a measured power conversion gain of 19 dB with a 3-dB bandwidth from 0.1 to 23 GHz, which is the highest gain-bandwidth product of operation among previously reported MMIC mixers. As an analog multiplier, the measured sensitivity is better than 3000 V/W from 0.1 to 25 GHz, and the measured low-frequency noise floor and corner frequency can be estimated to be 20 nV/sqrt(Hz) and 1.2 kHz, respectively. The mixer performance represents state-of-the-art result of the MMIC broad-band mixers using commercial silicon-based technologies     

RF noise in 0.18-/spl mu/m and 0.13-/spl mu/m MOSFETs

Studied the gate finger number and gate length dependence on minimum noise figure (NF/sub min/) in deep submicrometer MOSFETs. A lowest NF/sub min/ of 0.93 dB is measured in 0.18-/spl mu/m MOSFET at 5.8 GHz as increasing finger number to 50 fingers, but increases abnormally when above 50. The scaling gate length to 0.13 /spl mu/m shows larger NFmin than the 0.18-/spl mu/m case at the same finger number. From the analysis of a well-calibrated device model, the abnormal finger number dependence is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number. The scaling to 0.13-/spl mu/m MOSFET gives higher NF/sub min/ due to the higher gate resistance and a modified T-gate structure proposed to optimize the NF/sub min/ for further scaling down of the MOSFET.     

Compact 1.55 /spl mu/m room-temperature optically pumped VCSEL using photonic crystal mirror

Reported is the first realisation of a novel vertical cavity surface emitting laser (VCSEL), in which one of the Bragg mirrors is entirely replaced by a single-layer photonic crystal mirror (PCM). The presence of the PCM considerably enhances the vertical compactness of the device. Room-temperature singlemode laser emission has been obtained at 1.55 mum by optical pumping (pulsed regime), with a threshold power around 15 mW     

A two-step laterally tapered 1.55-/spl mu/m SSC DFB laser fabricated by using a nonselective grating process

We demonstrate a two-step laterally tapered 1.55-/spl mu/m spot size converter distributed feedback laser diode (SSC DFB LD) having a planar buried heterostructure-type active waveguide and a ridge-type passive waveguide fabricated by using a nonselective grating process. Unlike conventional SSC DFB LDs, where a selective grating is employed, this SSC DFB LD employed a nonselective grating over the entire device region in order to make its fabrication much simpler than that of the conventional SSC DFB LDs. The two-step laterally tapered SSC is effective in removing an unwanted wavelength peak originating from the SSC section having a multiquantum well and a grating under it. The fabricated SSC DFB LD operates at 1.553-/spl mu/m wavelength and shows a far field pattern in horizontal and vertical directions of 13.4/spl deg/ and 19.5/spl deg/, respectively.     

All-active tapered 1.55-/spl mu/m InGaAsP BH-DFB laser with continuously chirped grating

We demonstrate the first realization of all-active tapered index coupled 1.55-/spl mu/m InGaAsP buried-heterostructure distributed feedback lasers involving chirped gratings. The variation of the effective refractive index along the tapered active stripe is compensated using an optimized continuously chirped grating. The grating has been formed using a novel direct-write electron-beam lithography technique. Lasers with an antireflection/cleaved cavity show stable single-mode operation and high optical output power up to 60 mW. The yield of lasers with a sidemode suppression ration > 40 dB is more than 70%. The -3-dB farfield angles (full-width at half-maximum) amount to 14/spl deg/ and 20/spl deg/ in lateral and vertical direction, respectively.     

0.18-/spl mu/m nondestructive readout FeRAM using charge compensation technique

A nondestructive readout (NDRO) FeRAM using a 0.18-/spl mu/m CMOS technology has been developed. Readout voltages across the ferroelectric lower than the coercive voltage allowed the FeRAM to achieve high read endurance exceeding required performance for system LSIs, 10/sup 16/ read cycles. The NDRO approach uses a newly developed charge compensation technique to correct the process variations in threshold voltage of neighboring readout transistors, leading to a wide NDRO operation margin over a supply voltage range from 1.1 to 1.8 V.     

Bidirectional, subcarrier-multiplexed transmission using 1.3-/spl mu/m Fabry-Perot lasers

We demonstrate a full-duplex, subcarrier-multiplexed, transmission system which employs 1.3-/spl mu/m Fabry-Perot strained layer MQW laser diode transmitters in both directions. Coherent effects are reduced by using lasers with different mode spacing.     

MOVPE-grown GaInNAs VCSELs at 1.3 /spl mu/m with conventional mirror design approach

1.3 /spl mu/m oxide confined GaInNAs VCSELs designed using the same design philosophy used for standard 850 nm VCSELs is presented. The VCSELs have doped mirrors, with graded and highly doped interfaces, and are fabricated using production-friendly procedures. Multimode VCSELs (11 /spl mu/m oxide aperture) with an emission wavelength of 1287 nm have a threshold current of 3 mA and produce 1 mW of output power at 20/spl deg/C. The maximum operating temperature is 95/spl deg/C. Emission at 1303 nm with 1 mW of output power and a threshold current of 7 mA has been observed from VCSELs with a larger detuning between the gain peak and the cavity resonance.     

A 1-/spl mu/m Bipolar VLSI Technology

A 1-/spl mu/m VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 /spl mu/m. Both nonisolated I/sup 2/L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a seated LSI, I/sup 2/L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 /spl mu/m. Scaled SPB0400's have been fabricated that operate at clock speeds 3X higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I/sup 2/L and STL device designs. Power-delay products of 14 fJ for I/sup 2/L and 30 fJ for STL have been measured.     

Very-low-threshold, highly efficient, and low-chirp 1.55-/spl mu/m complex-coupled DFB lasers with a current-blocking grating

Low-threshold current DFB lasers have been fabricated based on a complex-coupled structure with a current blocking grating. A threshold current as low as 5 mA was obtained, which enabled high temperature operation up to 105/spl deg/C. Asymmetric facet coatings were applied to obtain a high efficiency of 0.3 W/A. The strained InGaAsP MQW active region and the antiphase coupling has resulted in a low modulation chirping. By direct modulation of the device at 2.488 Gb/s and using optical amplifiers, we have demonstrated digital transmission over a 235 km-long standard single-mode fiber with a power penalty of 1.55 dB.     

1.31-1.55-/spl mu/m phased-array demultiplexer on InP

The first demultiplexers on InP at 1.31-1.55 /spl mu/m based on low-order waveguide arrays have been fabricated and characterized. We show the calculated and measured spectral responses of two devices with 6 and 10 waveguides in the grating. The on-chip loss of the devices is 4.5 dB and the crosstalks are down to -25 dB. Thanks to their large bandwidth, the devices are polarization insensitive and no strong influence of the temperature is seen.     

A broad-band waveguide grating coupler with a subwavelength grating mirror

A new diffractive device for light coupling between a planar optical waveguide and free space is proposed. The device utilizes a second-order waveguide grating to diffract the fundamental waveguide mode into two free propagating beams and a subwavelength grating (SWG) mirror to combine the two free propagating beams into a single beam. The finite-difference time-domain (FDTD) simulations show that the SWG mirror improves the coupling efficiency of the waveguide fundamental mode into the single out-coupled beam from about 30% to 92%. A high efficiency (>90%) is predicted for a broad wavelength range of 1520-1580nm. The proposed device is compact (/spl sim/80 /spl mu/m in length) and it eliminates the need for blazing the waveguide grating.     

1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

Design methodology of a 1.2-/spl mu/m double-level-metal CMOS technology

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-/spl mu/m gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns, while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.     

A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.     

A Bluetooth radio in 0.18-/spl mu/m CMOS

This paper describes the results of an implementation of a Bluetooth radio in a 0.18-/spl mu/m CMOS process. A low-IF image-reject conversion architecture is used for the receiver. The transmitter uses direct IQ-upconversion. The VCO runs at 4.8-5.0 GHz, thus facilitating the generation of 0/spl deg/ and 90/spl deg/ signals for both the receiver and transmitter. By using an inductor-less LNA and the extensive use of mismatch simulations, the smallest silicon area for a Bluetooth radio implementation so far can be reached: 5.5 mm/sup 2/. The transceiver consumes 30 mA in receive mode and 35 mA in transmit mode from a 2.5 to 3.0-V power supply. As the radio operates on the same die as baseband and SW, the crosstalk-on-silicon is an important issue. This crosstalk problem was taken into consideration from the start of the project. Sensitivity was measured at -82 dBm.     

High-power 2.3-/spl mu/m GaSb-based linear laser array

High-power 2.3-/spl mu/m In(Al)GaAsSb-GaSb type-I double quantum-well diode laser arrays were fabricated and characterized. Linear laser arrays with 19 100-/spl mu/m-wide elements on a 1-cm-long bar generated 10 W in continuous-wave (CW) mode and 18.5 W in quasi-CW mode (30 /spl mu/s/300 Hz) at a heatsink temperature of 18/spl deg/C. Array power conversion efficiency peaked at 30 A and was about 9%. Device internal efficiency was about 50%. Individual laser differential gain with respect to current was about twice as high as in InP-based laser heterostructures, demonstrating the potential of GaSb-based material system for high-power CW room-temperature laser diode arrays.     

A 0.18-/spl mu/m CMOS bioluminescence detection lab-on-chip

The paper describes a bioluminescence detection lab-on-chip consisting of a fiber-optic faceplate with immobilized luminescent reporters/probes that is directly coupled to an optical detection and processing CMOS system-on-chip (SoC) fabricated in a 0.18-/spl mu/m process. The lab-on-chip is customized for such applications as determining gene expression using reporter gene assays, determining intracellular ATP, and sequencing DNA. The CMOS detection SoC integrates an 8 /spl times/ 16 pixel array having the same pitch as the assay site array, a 128-channel 13-bit ADC, and column-level DSP, and is fabricated in a 0.18-/spl mu/m image sensor process. The chip is capable of detecting emission rates below 10/sup -6/ lux over 30 s of integration time at room temperature. In addition to directly coupling and matching the assay site array to the photodetector array, this low light detection is achieved by a number of techniques, including the use of very low dark current photodetectors, low-noise differential circuits, high-resolution analog-to-digital conversion, background subtraction, correlated multiple sampling, and multiple digitizations and averaging to reduce read noise. Electrical and optical characterization results as well as preliminary biological testing results are reported.     

K-band low-noise amplifiers using 0.18 /spl mu/m CMOS technology

Two K-Band low-noise amplifiers (LNAs) are designed and implemented in a standard 0.18 /spl mu/m CMOS technology. The 24 GHz LNA has demonstrated a 12.86 dB gain and a 5.6 dB noise figure (NF) at 23.5 GHz. The 26 GHz LNA achieves an 8.9 dB gain at the peak gain frequency of 25.7 GHz and a 6.93 dB NF at 25 GHz. The input referred third-order intercept point (IIP3) is >+2 dBm for both LNAs with a current consumption of 30 mA from a 1.8 V power supply. To our knowledge, the LNAs show the highest operation frequencies ever reported for LNAs in a standard CMOS process.