A buck quadratic PWM soft-switching converter using a single activeswitch

High-switching frequency associated with soft commutation techniques is a trend in switching converters. Following this trend, a buck pulsewidth modulation (PWM) converter is presented. The DC voltage conversion ratio of this converter has a quadratic dependence on duty cycle, providing a large stepdown. This new buck quadratic PWM soft-single-switched converter, having only a single active switch, provides a high efficient operating condition for a wide load range at high-switching frequency. In order to illustrate the operating principle of this new converter, a detailed study including theoretical analysis, relevant equations and simulation, and experimental results is carried out     

A quadratic buck converter with lossless commutation

High switching frequency associated with soft commutation techniques is a new trend in switching converters. Following this trend, the authors present a buck pulsewidth modulation converter, where the DC voltage conversion ratio has a quadratic dependence on duty cycle, providing a large step-down. By introducing two resonant networks, soft switching is attained, providing highly efficient operating conditions for a wide load range at high switching frequency. Contrary to most of the converters that apply soft-switching techniques, the switches presented are not subjected to high switch voltage or current stresses and, consequently, present low conduction losses. The authors present, for this converter, the principle of operation, theoretical analysis, relevant equations and simulation and experimental results     

Digital control of a voltage-mode synchronous buck converter

A digital control algorithm capable of separately specifying the desired output voltage and transient response for a synchronous buck converter operating in voltage mode was developed. This algorithm is based on superimposing a small control signal onto a voltage reference at each switching cycle to cancel out the perturbations. A zero steady-state error in the output voltage can be obtained with the aid of additional dynamics to allow the controller to track a load change and update the reference to a new load state. The specifications of the control algorithm are achieved by pole placement using complete state feedback. The control algorithm was implemented on a digital signal processor (DSP)-controlled synchronous buck converter.     

一种Buck变换器中的误差放大器设计

基于系统稳定性的分析和负载瞬态响应的需求,本文设计了一种用于电流模式恒定导通时间(COT)架构DC-DC降压Buck变换器的高性能误差放大器并提出系统补偿方案。该误差放大器在保证频率特性良好的同时,具备高增益、补偿网络简单的优点。文中对所提出的电路结构以及系统补偿方案进行了详细的说明与理论推导,并使用Simplis软件对系统相位裕度进行仿真,最后基于0.18μm BCD(Bipolar CMOS DMOS)工艺,使用Hspice软件对电路进行了仿真验证。仿真结果表明:电源电压为2.7～5.5 V、输出电压为1.8 V时,系统的相位裕度位于62.5°到69.3°之间,负载瞬态恢复时间最大仅为17.3μs。     

同步整流Buck变换器的损耗分析

文中在以往只粗略计算电感损耗、电容损耗及开关损耗的基础上,以一款低电压大电流同步整流降压变换器为例,详细分析了各个元器件上功率损耗,包括电感上的铜损与铁损,电容等效串联电阻的损耗,MOSFET上的开关损耗、导通损耗、截止损耗、驱动损耗、寄生体二极管损耗等,从而得到直流降压变换器的整体损耗与实际效率。从效率曲线可以看出,变换器效率随着输出电流的增加而增加,并很快趋于饱和。而通过损耗分析可知,要降低损耗提高效率,尤其对于低电压大电流输出的降压变换器,不仅可以采用同步整流技术来降低导通压降,还可以根据各损耗所占比重大小选用更优元器件,如低直流电阻的电感,低导通电阻、低上升下降时间的NMOS管等。     

50 MHz dual-mode buck DC-DC converter

A 50 MHz 1.8/0.9 V dual-mode buck DC-DC converter is proposed in this paper. A dual-mode control for high-frequency DC-DC converter is presented to enhance the conversion efficiency of light-load in this paper. A novel zero-crossing detector is proposed to shut down synchronous rectification transistor NMOS when the inductor crosses zero, which can decrease the power loss caused by reverse current and the trip point is adjusted by regulating IBIAS (BIAS current). A new logic control for pulse-skipping modulation loop is also presented in this paper, which has advantages of simple structure and low power loss. The proposed converter is realized in SMIC 0.18 μm 1-poly 6-metal mixed signal CMOS process. With switching loss, conduction loss and reverse current related loss optimized, an efficiency of 57% is maintained at 10 mA, and a peak efficiency of 71% is measured at nominal operating conditions with a voltage conversion of 1.8 to 0.9 V.     

A zero-voltage-switched three-phase interleaved buck converter

This paper proposes a three-phase interleaved buck converter which is composed of three identical paralleled buck converters. The proposed solution has three shunt inductors connected between each other of three basic buck conversion units. With the help of the shunt inductors, the MOSFET parasitic capacitances will resonate to achieve zero-voltage-switching. Furthermore, the decreasing rate of the current through the free-wheeling diodes is limited, and therefore, their reverse-recovery losses can be minimised. The active power switches are controlled by interleaved pulse-width modulation signals to reduce the input and output current ripples. Therefore, the filtering capacitances on the input and output sides can be reduced. The power efficiency is measured to be as high as 98% in experiment with a prototype circuit.     

Bifurcation behavior of the buck converter

The DC-DC buck power converter, a widely used chopper circuit, exhibits subharmonics and chaos if current feedback is used. This paper investigates the dependence of the system behavior on its parameters. The bifurcation phenomena and a mapping of the parameter space have been presented. This knowledge is vital for designing practical circuits     

Synthetic-ripple modulator for synchronous buck converter

Comprising a hysteretic comparator and a ripple synthesizer, the synthetic-ripple modulator (SRM) allows voltage-hysteretic modulation to be realized in low-voltage buck converters where the natural voltage ripple is too small for reliable hysteretic operation. Circuit implementation, steady-state operation, and design equations are described for an SRM controlling a buck dc-dc converter. The basics are verified experimentally by a buck converter switched at 420 kHz and delivering 10 A at 1.8 V.     

Wireless PWM control of a parallel DC-DC buck converter

We demonstrate a new concept for wireless pulse-width modulation (PWM) control of a parallel dc-dc buck converter. It eliminates the need for multiple physical connections of gating/PWM signals among the distributed converter modules. The new scheme relies on radio-frequency (RF) based communication of the PWM control signals from a master to the slave modules. We analyze the system stability and demonstrate the experimental effectiveness of the wireless control scheme for a two-module parallel buck converter for 10-kHz and 20-kHz switching frequencies and for channel lengths of 1.5 and 15ft, respectively. The proposed control concept may lead to easier distributed control implementation of parallel dc-dc converters and distributed power systems, and may lead to redundancy that is achievable using droop method. It may also be used as a backup for wire-based control of parallel converters to provide fault tolerance.     

Analysis of a four-level DC/DC buck converter

In this paper, a four-level DC/DC buck power converter is introduced. The primary application for this converter is to regulate the center capacitor voltage in a four-level inverter system. The steady-state and average-value models for the proposed converter are developed and compared in simulation. The converter was constructed in the laboratory and verified on a four-level motor drive system. It was shown that the four-level DC/DC converter provides capacitor voltage balancing and allows higher output voltage utilization from the inverter.     

一种具有动态零点补偿的电流模DC-DC降压型转换器

To achieve fast transient response for a DC-DC buck converter,an adaptive zero compensation circuit is presented.The compensation resistance is dynamically adjusted according to the different output load conditions, and achieves an adequate system phase margin under the different conditions.An improved capacitor multiplier circuit is adopted to realize the minimized compensation capacitance size.In addition,analysis of the small-signal model shows the correctness of the mechanism of the proposed adaptive zero compensation technique.A currentmode DC-DC buck converter with the proposed structure has been implemented in a 0.35μm CMOS process,and the die size is only 800×1040μm~2.The experimental results show that the transient undershoot/overshoot voltage and the recovery times do not exceed 40 mV and 30μs for a load current variation from 100 mA to 1 A.     

A 400-mA current-mode buck converter with a self-trimming current sensing scheme

A current-programmed mode (CPM) controller is designed for improved DC–DC converter control. The key building block of the CPM controller is an accurate current-sensing circuit. This paper proposes a lossless current-sensing technique to measure the inductor current by measuring the current through the power transistor. A self-trimming circuit is used to compensate for any inaccuracies caused by voltage and temperature variations. The measurement results validate the operation of the fabricated chip.     

适用于具有自适应续流电流的单电感双输出降压变换器的准滑模控制器设计

An analog implementation of a novel fixed-frequency quasi-sliding-mode controller for single-inductor dual-output(SIDO) buck converter in pseudo-continuous conduction mode(PCCM) with a self-adaptive freewheeling current level(SFCL) is presented.Both small and large signal variations around the operation point are considered to achieve better transient response so as to reduce the cross-regulation of this SIDO buck converter.Moreover,an internal integral loop is added to suppress the steady-state regulation error introduced by conventional PWM-based sliding mode controllers.Instead of keeping it as a constant value,the free-wheeling current level varies according to the load condition to maintain high power efficiency and less cross-regulation at the same time.To verify the feasibility of the proposed controller,an SIDO buck converter with two regulated output voltages,1.8 V and 3.3 V,is designed and fabricated in HEJIAN 0.35 m CMOS process.Simulation and experiment results show that the transient time of this SIDO buck converter drops to 10 s while the cross-regulation is reduced to 0.057 mV/mA,when its first load changes from 50 to 100 mA.     

A zero-current-switching PWM flyback converter with a simpleauxiliary switch

A simple and effective approach of turning an isolated hard-switched converter design into a soft-switched one is presented. By adding an auxiliary winding, switch and small capacitor to the conventional pulsewidth modulation (PWM) isolated flyback converter, all switches and diodes are softly turned on and off. No extra active or passive voltage clamp circuit is needed to suppress voltage stress on the switching devices that were usually found in classical converters. A zero-current-switching (ZCS) PWM flyback converter topology with multiple outputs is analyzed and examined. The proposal inherently utilizes the leakage inductance of the “flyback” transformer to achieve ZCS of all switching devices. A complete steady-state DC analysis and the operating principle are described. The performance of an 80 W experimental converter prototype with dual-voltage outputs is included     

Posicast-based digital control of the buck converter

The analysis, design, and microcontroller-based implementation of a digital controller using a Posicast element are presented for the buck converter. Posicast is a feedforward compensator that eliminates overshoot in system response, but the traditional approach is sensitive to variations in natural frequency. The new method described here reduces the undesirable sensitivity by using Posicast within a feedback loop. Compared to classical proportional-integral-derivative (PID) control, the new control results in lower noise in the control signal because the controller has a lower gain at high frequency. Furthermore, the authors' experiments indicate that the new controller is less sensitive to the inherent time delay associated with a digital controller for a dc-dc converter. The authors present a straightforward method to design controller parameters from the small-signal averaged model of the converter dynamics. Experimental results for a PID-controlled converter and Posicast-type controller are also compared.     

Reconfigurable digital controller for a buck converter based on FPGA

This paper presents a complete digitally controlled dc–dc buck converter performed by FPGA circuitry. All tasks, analog to digital conversion, control algorithm and pulse width modulation, were implemented in the FPGA. This approach enables high-speed dynamic response and programmability by the controller, without external passive components. In addition, the controller’s structure can be easily changed without external components. The applied algorithm enables a switching frequency of 100 kHz.     

Tapped-inductor buck converter for high-step-down DC-DC conversion

The narrow duty cycle in the buck converter limits its application for high-step-down dc-dc conversion. With a simple structure, the tapped-inductor buck converter shows promise for extending the duty cycle. However, the leakage inductance causes a huge turn-off voltage spike across the top switch. Also, the gate drive for the top switch is not simple due to its floating source connection. This paper solves all these problems by modifying the tapped-inductor structure. A simple lossless clamp circuit can effectively clamp the switch turn-off voltage spike and totally recover the leakage energy. Experimental results for 12V-to-1.5V and 48V-to-6V dc-dc conversions show significant improvements in efficiency.     

一种新型软开关BUCK变换器

根据传统硬开关电源引起的不良影响,提出了一种新型软开关BUCK变换器,使得高低桥MOSFET管都能在不管是轻负载或者重负载情况下达到ZVS状态.在连续导电模式（CCM）和高负载电流情况下,上桥MOSFET管开通,下桥MOSFET管侧的二极管在死区时间内导电,这样就造成了上桥MOSFET管的开关损耗.新型软开关BUCK变换器在传统BUCK变换器的基础上加入了电感和电容,在外加电感电容的情况下,在CCM下的死区时间内的电感电流可以有效地从下桥二极管整流到上桥二极管中.根据仿真结果和工作模式分析验证其性能.     

Automotive DC-DC bidirectional converter made with many interleaved buck stages

Interleaving technique is used in some applications due to its advantages regarding filter reduction, dynamic response, and power management. In dual battery system vehicles, the bidirectional dc-dc converter takes advantage of this technique using three-to-five paralleled buck stages. In this paper, we propose the use of a much higher number of phases in parallel together with digital control. It will be shown that this approach opens new possibilities since changes in the technology are possible. Thus, two 1000-W prototypes have been designed using surface mount technology devices (SO-8 transistors). An additional important feature is that due to the accuracy of the digital device [field-programmable gate array (FPGA)], current loops have been eliminated, greatly simplifying the implementation of the control stage.