一种昼夜兼容成像EMCCD图像传感器

本文设计制作了一款阵列规模为1024×1024元、像元尺寸为10μm×10μm的昼夜兼容成像EMCCD(electron multiplying charge coupled device),该器件包含国内首次制作的浮置栅放大器,该放大器电荷转换因子(Charge to voltage factor,CVF)为3.57μV/e^-,满阱55 ke^-,能够非破坏性判断信号强度。该功能使得场景中微光照区域的像素可以选择性地路由至倍增通道输出,而强光照区域的像素会路由至非倍增通道输出,有了这种场景内可切换增益特性,两种输出的信号重新组合,实现高动态成像。同时为了实现器件在强光应用场合的抗光晕功能,器件像元区域采用了纵向抗晕设计,抗晕倍数为200倍,基于此类器件制作的相机能够恰当地在暗视场中呈现明亮的图像。     

Bypassing omega network for high speed packet switching

A highly regular switching network consisting of several switching stages for output buffering is proposed. Each switching element performs 3×3 switching and has a tail-spared buffer for each input port. According to the performance evaluation of the proposed switching network based on computer simulation, a packet loss ratio of 10^-8 was obtained for a 1024×1024 switching network consisting of 15 stages with the Bernoulli traffic source when the size of tail-spared buffer is 8 and the input traffic load is 0.9     

A Knockout Switch for Variable-Length Packets

The Knockout Switch is a new packet switch architecture recently proposed for high-speed local and metropolitan area networks, multiprocessor interconnects, and local or toll switches for integrated traffic loads. We describe an approach to extend the original Knockout Switch to work with variable-length packets. This new architecture employs an input broadcast bus arrangement to achieve complete interconnection of the inputs and outputs. Consequently, there is no congestion in the switch fabric other than the unavoidable conflict of multiple simultaneous packets destined for the same output. It is with this output contention that the Knockout principle is fully utilized to efficiently concentrate and store contending packets while maintaining the first-in first-out discipline of the packet sequence; and yet the fabric speed required is no more than the input/output line speeds, Under these design goals, no switch can yield better delay/ throughout performance. These are the most important attributes that have been preserved in the current proposal from the original Knockout Switch. For anN times Nswitch configuration, the variable-length packet Knockout Switch consists ofNinput broadcast buses, and anN:Lconcentrator (L ll N) and a shared buffer for each output. The design of each subsystem is discussed with emphasis on possible VLSI realization. Using today's technology, we should be able to implement the proposed switch with both input/output lines and internal hardware operating at 50 Mbits/s. The dimension of the switch (N times N) can grow modularly from say 32 × 32 to 1024 × 1024, rendering a total throughput in the range of tens of gigabits per second. Future upgrading of the line interfaces to much higher speed without modification to the internal switch hardware is also possible with a modest restriction on the minimum length of new packets.     

CCD MPP结构制作工艺技术研究

在1024×1024可见光电荷耦合器件(CCD)的基础上增加了MPP(Multi-PinnedPhase)结构设计和工艺制作.制得的1024×1024可见光MPP CCD实现了MPP功能,有效抑制了CCD表面暗电流的产生.当MPP注入剂量为(6±2)×10~(11)cm~(-2)时,其暗电流密度下降了2/3,满阱电荷下降了1/2.

Abstract：

Multi-Pinned Phase (MPP) structure is designed and fabricated on the base of 1024×1024 visible light CCD. The 1024×1024 visible light MPP CCD achieves MPP function and suppresses the surface dark current effectively. Its dark current density and full well capacity decrease 2/3 and 1/2, respectively, when MPP implant dose is(6±2)×10~(11) cm~(-2).     

一种基于FPGA的高性能FFT处理器设计

FFT算法是高速实时信号处理的关键算法之一,在数字EW接收机中有着广泛的应用前景。本文基于Xilinx公司的Vertex-IIPro系列FPGA,设计一种级联结构的1024点FFT处理器,采用基-4并行蝶算单元,能并行处理四路输入数据,极大地提高了FFT的处理速度。在系统时钟为100MHz时,完成1024点复数FFT运算仅需要2.56μs。     

Fast transmission distortion estimation and adaptive error protection for H.264/AVC-based embedded video conferencing systems

This paper presents the design and implementation of an error-resilient H.264/AVC-based embedded video conferencing scheme over Internet. We first develop a fast recursive algorithm to estimate the decoder-side distortion of each frame in the presence of packet loss. The algorithm operates at block level, and considers the impacts of different intra prediction modes, the unrestricted intra prediction, and the skip mode. We then design a family of very short systematic forward error correction codes with linear encoding and decoding complexity, which runs across the slices of each frame to recover lost packets. An optimization problem is then formulated to minimize the decoder-side distortion by allocating a given channel coding redundancy among a group of frames. Various techniques are introduced to speed up the algorithm without sacrificing too much accuracy, in order to meet the hardware and real-time constraints of the system. As a result, the proposed scheme can run on a real-time embedded video conferencing system with resolution up to 1024×576 pixels, 30 frames per second (fps) and 4 megabits per second (Mbps).     

Recent data on image enhancement programs

Some internal input-output differences between the CDC 6600 and 7600 computers are reviewed, along with the effect of those differences on programs for enhancing large images (1024 by 1024 matrix). Recent data from a program for the CDC 7600 are presented, showing a factor of 5 greater speed over a previously reported program.     

A 1024-QAM Analog Front-End for Broadband Powerline Communication Up to 60 MHz

A high performance analog front-end (AFE) for broadband powerline communication between 1.6 and 60 MHz is presented. The frequency division multiplexing AFE supports optimum channel selection, avoids disturbing RF signals and allows co-existence with other users of the spectrum. The direct-conversion receiver operates linearly up to a + 18 dBm input level. Tunable low-pass filters, integrated into the receive path, support a wide class of service requirements by channel bandwidth selection. The dynamic range is 99.5 dB for 2 MHz channels, and 90.5 dB for 16 MHz channels. Error vector magnitude measurements are presented for a single-carrier 1024-QAM and a 1024-carrier 64-QAM signal as function of frequency and channel attenuation. For 1024-QAM, the error vector magnitude (EVM) is below or equal to 1.2% rms up to 60 dB of attenuation, whereas the 1024-carrier 64-QAM performs well up to 80 dB of attenuation. The presented chip was fabricated in a 0.25 mum SiGe BiCMOS process, and the measured power consumption from a single 2.5 V supply is 668 mW.     

1兆位3伏闪速电擦除16位存储器AT29LV1024及其应用

AT29LV1024是ATMEL公司推出的3V闪速电擦除存储器(EEPROM),它采用ATMEL公司先进的非易失性的COMS工艺制造,可快速准确地实现数据的存储。因此,它可应用于各种单片机系统。     

RSFQ 1024-bit shift register for acquisition memory

Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of ±23% and ±14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO_x /Nb process with a junction critical current density of 1.0 kA/cm ²     

1024-QAM and 256-QAM Coded Modems for Microwave and Cable System Applications

Low redundancy FEC coded 1024-QAM modems, staggered 1024-QAM, and 256-QAM modems for spectrally efficient (up to 8.84 bits/s/Hz) microwave and cable systems applications are described. Such a high spectral efficiency is required for CEPT-1 (2.048 Mbit/s) rate digital transmission in a single analog supergroup (SG` band as well as for other emerging systems applications. Practical constraints of operational analog FDM systems are presented and taken into account in the choice of the low redundancy FEC codec and the coded 1024-QAM modem. Theoretical, computer simulation and experimental results of 256QAM modems have been extended to the feasibility study of 512-QAM, 961-QPRS, and 1024-QAM modems. Our experience with 256-QAM modems which have a T-1 (1.544 Mbit/s) rate in a 240 kHz analog supergroup (SG) band, i.e., an efficiency of 6.66 bits/s/Hz, demonstrates that a regenerative span over 1000 km is feasible over FDM radio systems. A significantly increased spectral efficiency of 8.84 bits/s/Hz is required for CEPT-1/SG system applications. Our R&D results, presented in this paper, demonstrate the feasibility of FEC coded 1024QAM modems, equipped with powerful digital adaptive equalizers, carrier phase noise, and symbol clock jitter cancellation subsystems, for the transmission of CEPT-1 rate signals in a single SG band.     

CMOS器件光学特性的测量

介绍了一种测量CMOS像感器调制传递函数(modulation transfer function,MTF)的方法,分别构造了可用于MTF和光谱量子效率测量的实验系统.并利用上述实验系统对1024×1024的CMOS像感器的MTF和量子效率进行了测量,获得了令人满意的结果.     

RSA密码协处理器的实现

密码协处理器的面积过大和速度较慢制约了公钥密码体制RSA在智能卡中的应用.文中对Montgomery模乘算法进行了分析和改进,提出了一种新的适合于智能卡应用的高基模乘器结构.由于密码协处理器采用两个32位乘法器的并行流水结构,这与心动阵列结构相比它有效地降低了芯片的面积和模乘的时钟数,从而可在智能卡中实现RSA的数字签名与认证.实验表明:在基于0.35μm TSMC标准单元库工艺下,密码协处理器执行一次1024位模乘需1216个时钟周期,芯片设计面积为38k门.在5MHz的时钟频率下,加密1024位的明文平均仅需374ms.该设计与同类设计相比具有最小的模乘运算时钟周期数,并使芯片的面积降低了1/3.这个指标优于当今电子商务的密码协处理器,适合于智能卡应用.     

一种应用于CMOS图像传感器的片上内插式ADC设计

设计了一种用于1024×1024CMOS图像传感器的内插式模数转换器（ADC）结构。转换采用并行处理方式,采用内插式结构,与流水线ADC相比速度更快。电路采用失调纠正技术和衬底驱动技术设计了1个低失调电压的前置全差分两级跨导运算放大器（OTA）,PMOS管作为电阻产生与锁存阈值电压相交的基准电压,具有较高的精度。基于0．35μmCMOS工艺的仿真结果表明,该ADC的DNL=0．45LSB,INL=0．65LSB,可以满足CMOS图像传感器芯片级ADC的高速高精度要求。     

高速Cameralink图像数据光纤传输系统设计

Cameralink接口是目前工业数字相机的主要图像输出接口。但受传输距离限制,在远程视频网络中,图像数据一般以光信号传输。针对Cameralink接口相机在光纤网络中应用的这一具体问题,对Cameralink接口光纤传输系统进行了研究。设计的传输系统可兼容多种像素时钟的相机,最高传输带宽达到1.92Gb/s,可满足1024×1024相机100帧/秒拍摄频率下的数据量要求。     

双线性插值算法的优化及其应用

针对双线性插值算法作为视频缩放算法,硬件实现面积大、功耗高、速度慢的不足,提出了逆向映射法对图像进行映像,并对取整取小数算法进行简化,同时进一步对算法中的乘法运算进行优化,改进后的双线性插值算法实现的硬件电路面积更小,功耗更低,处理能力更强。在180 nm CMOS工艺下进行了逻辑综合和仿真,实验结果表明,时钟频率为100 MHz时,面积为148千门,能够满足H.264高清(1 024×1 024)30 f/s的视频缩放。     

基于FPGA的多通道面阵CCD成像系统设计

以Sarnoff公司的CCD图像传感器VCCD1024H作为敏感元件,设计了一种基于FPGA的多通道面阵CCD成像系统,介绍了CCD工作原理、成像系统总体结构、各部分硬件电路、工作模式及FPGA时序逻辑设计,讨论了成像时序和数据整合。通过仿真验证FPGA逻辑满足成像及数据传输要求,为后续应用奠定了基础。     

JAGUAR: a fully pipelined VLSI architecture for JPEG imagecompression standard

In this paper, we describe a fully pipelined single chip VLSI architecture for implementing the JPEG baseline image compression standard. The architecture exploits the principles of pipelining and parallelism to the maximum extent in order to obtain high speed and throughput. The architecture for discrete cosine transform and the entropy encoder are based on efficient algorithms designed for high speed VLSI implementation. The entire architecture can be implemented on a single VLSI chip to yield a clock rate of about 100 MHz which would allow an input rate of 30 frames per second for 1024×1024 color images     

高速芯片设计中时序的研究

高速芯片设计中所有时序的容差都非常小,而互连延迟在整个时序预算中所占的比例随着速度的升高而变大。因此为了满足其高速性能,一方面要精确地定位电路各部分的延迟模,另一方面必须把实际布图后互连延迟信息返标到逻辑综合环境。文章结合ＢＡＰ１０２４芯片的设计,对这方面进行了研究。     

基于CPLD的CMOS APS驱动时序的设计

详细介绍了Photobit公司的PB-1024CMOS APS图像传感器的驱动时序关系,提出了基于CPLD来实现CMOS APS图像传感器驱动控制电路的方法。系统选用美国Xilinx公司的XC9500系列CPLD作为硬件设计的开发平台,运用VHDL语言来实现对驱动电路的硬件描述,并采用Xilinx公司的Foundation软件对设计的驱动时序进行了仿真。测试与仿真结果表明所设计的驱动时序电路完全能够达到CMOS APS图像传感器的要求。