Fast electromigration wafer mapping for wafer fab process monitoring and improvement

In this work, a set up for fast wafer level electromigration (WL-EM) is developed with the use of a standard electrical analyser, a semi-auto probe station with a hot chuck, and a PC. EM tests on multiple test structures are carried out simultaneously and tests are done at multiple locations (EM mapping) across the wafer. Measured data are imported into MS EXCEL and analysed with a macro automatically. Good correlations are demonstrated between the fast WL-EM test and classical package level EM at 0.1% failure rate. For several years reliable EM monitoring charts are created with the fast WL-EM set up. The fast EM mapping test does not only exploit the advantages of fast WL-EM test in terms of short throughput time and low cost (without packaging) for process monitoring, the additional information on EM performance across the wafer makes the test extremely valuable for process improvement.     

Simulation tool for design and management optimization of automatedinterbay material handling and storage systems for large wafer fab

The ever-increasing need to introduce in Wafer Fab automated handling and storage systems, requires reliable design and performance analysis tools. In this paper a simulation model, able to represent both the handling and storage devices and the Wafer Fab production progress, is presented. The process dynamic is approached by generalized probability density functions linked only to global process parameters (i.e. throughput time, theoretical cycle times), that may be a priori known. The methodology is tested with reference to a large Wafer Fab recently installed in Italy by Texas Instruments     

Automation and fab concepts for 300 mm wafer manufacturing

The introduction of 300 mm wafers into integrated circuit manufacturing will affect the design of the fabs. This paper covers the expectations of IC manufacturers and the progress in technology with respect to the fab itself and automation systems. The fab design is affected by the future use of closed wafer carriers, a consequent automation strategy, new challenges in contamination control, and the increased importance of environmental aspects. It will be described how these factors influence the fab design and the status of the discussed technologies.     

半导体晶圆车间的成本控制方法

由于市场对专用集成电路需求的猛增，大多数半导体企业都已采用面向订单的混合生产方式，其车间设施具有一定的柔性，能同时生产多种类型的晶圆；再加上CIM与价格昂贵、自动化程度极高的晶圆加工设备的广泛运用，引起了晶圆车间成本构成中直接人工费用大幅度减少和间接费用呈多样化巨增，因此晶圆制造车间已开始改变为从工程学、技术层向去把握成本信息，以工程经济学的方法对成本进行预测、监控，因为在晶圆制造车间中，成本绝非单纯是会计帐簿上的产物，而是在制造过程中的逐道工序中产生的。     

Applying just-in-time in a wafer fab: a case study

The successful application of the just-in-time (JIT) manufacturing management philosophy within a wafer fab photoresist wet chemistry area is described. The JIT techniques that were applied included lot-size reduction, setup-time reduction, layout changes for improved work flow, and improved operator flexibility. These set the stage for the implementation of a demand-pull system that resulted in significant decreases in cycle times as well as corresponding decrease in inventory levels. Aspects related to quality improvement as well as other long-term issues are also discussed     

Optimizing multichamber work cell management: an application to aDRAM wafer fab

The management of a work cell consisting of multichamber systems Endura 5500 PVD is addressed with the goals of maximizing production volume and facilitating maintenance plans. These objectives are pursued through suitable system configuration and loading. A mixed integer linear programming model incorporating such requirements as workload equalization and fault tolerance is devised to find optimal chamber assembly. The nominal productivity under distinct feasible production modes is evaluated by simulating Endura operation scheduling, and then utilized as problem input to compute nominal work cell productivity under steady-state inventory conditions. This method has been successfully adopted in an actual wafer fab to determine sputtering capacity allocation     

Lithographyless ion implantation technology for agile fab

A new type of ion implanter developed for an agile fab can eliminate the processes concerned. with photoresist lithography from the ion implantation process. This new ion implantation technology can reduce the raw process time, footprint, and the cost of ownership to less than one-half that of conventional ion implantation technology. The authors are making further developments on this ion implanter and evaluating technical issues related to ion implantation. This technique is suitable for manufacturing submicron node IC devices. Based on the results of evaluating the prototype machine, we will produce the next /spl beta/-machine.     

Warpage simulation for the reconstituted wafer used in fan-out wafer level packaging

Fan-out packaging technology involves processing redistribution interconnects on reconstituted wafer, which takes the form of an array of silicon dies embedded in epoxy molding compound (EMC). Yields of the redistribution interconnect processes are significantly affected by the warpage of the reconstituted wafer. The warpage can be attributed to the crosslinking reaction and viscoelastic relaxation of the EMC, and to the thermal expansion mismatch between dissimilar materials during the reconstitution thermal processes. In this study, the coupled chemical-thermomechanical deformation mechanism of a commercial EMC was characterized and incorporated in a finite element model for considering the warpage evolution during the reconstitution thermal processes. Results of the analyses indicate that the warpage is strongly influenced by the volume percentage of Si in the reconstituted wafer and the viscoelastic relaxation of the EMC. On the other hand, contribution from the chemical shrinkage of the commercial EMC on warpage is insignificant. As such, evaluations based on the comprehensive chemical-thermomechanical model considering the full process history can be approximated by the estimations from a simplified viscoelastic warpage model considering only the thermal excursion.     

The parylene-aluminum multilayer interconnection system for wafer scale integration and wafer scale hybrid packaging

Polyimides have been considered as interlayer dielectrics for wafer scale integration (WSI) and wafer scale hybrid packaging (WSHP). However, high temperature curing steps for polyimide lead to large stresses in polyimide films. This is due to differing thermal expansion coefficients of the metal conductor, insulator and substrate materials causing yield and reliability problems. Polyimides also require the use of solvents, and tend to outgas during subsequent processing. They tend to absorb moisture with resulting degradation of dielectric constants. Also, the spin on method used to apply and planarize polyimide layers exhibits nonuniformity of thickness on large wafers. In this paper we examine parylene (Poly-p-xylylene) and some of its derivatives as possible interlayer dielectrics due to some of their attractive features. Parylene has a low dielectric constant. It can be vapor deposited at low temperatures and in vacuum. It is also highly resistant to corrosion and is a clear, transparent material with possible use for optical interconnections. This paper studies the reactive ion etching properties for polyimides and parylenes in an oxygen containing plasma under identical conditions. The etching rates of the parylenes and polyimides have been compared. The surface properties of these polymers are examined. Further, the film growth properties of aluminum deposited on the etched surfaces using the ionized cluster beam are investigated.     

Mechanisms of wafer sawing and impact on wafer properties

Silicon wafer wire‐sawing experiments were realized with different sets of sawing parameters, and the thickness, roughness, and cracks depth of the wafers were measured. The results are discussed in relation to assumptions underlying the rolling–indenting model, which describes the process. It was also found that the silicon surface at the bottom of the sawing groove is different from the wafer surface, implying different sawing conditions in the two positions. Furthermore, the measured parameters were found to vary along the wire direction, between the entrance of the wire in the ingot and its exit. Based on these observations, some improvements for the wire‐sawing model are discussed. Copyright © 2010 John Wiley & Sons, Ltd.     

High-speed AMHS and its operation method for 300-mm QTAT fab

By using all-single-wafer processing in the 300-mm quick turn-around time production system, we have shortened cycle time to one-half or less than that of mixed-batch processing. We have also developed a high-speed automated material handling systems (AMHS) for achieving short cycle time. An intrabay rail-guided vehicle developed for the 300-mm fab is a component of this system. This paper describes the new system concepts, including AMHS hardware improvement, operation methods, and technician skill enhancement. We achieved a transfer time of one third or less that of previous fabs.     

New microcharacters for wafer identification

Conventional identification (ID) systems use characters that are often illegible, with character recognition being difficult in as many as 20% of all processes. In contrast, new microcharacters in the V-shaped notch are clearly recognized throughout the process. The results can be explained by the following multiple effects. Marking location: These markings require only a small space. Hence, markings can even be in the beveled section of the V-shaped notch of a wafer. In the case of conventional ID systems, it is difficult to select an area that gives good readability during processes and wide enough for marking. Dot topography: A marking dot formed by conventional laser marking has a central depression due to the process of general heat distribution. In contrast, a marking dot formed by micro marking has a central peak protruding from the surface that is more easily distinguished than a dot that has a central depression. The contrast of the new dot is about two times greater than that of a conventional one. Contrast greatly influences readability