Automatic start-up technique for complementary PTAT current generators

An automatic start-up technique for a class of bipolar analogue IC complementary current, or voltage, generators known as PTAT (proportional to absolute temperature) is proposed and its potentialities discussed.     

Current-mode analogue interface for high-speed low-current differential signalling

In this work, we propose high-speed low-current differential signalling (LCDS) over an electrical chip-to-chip interconnect by using a common-gate transimpedance amplifier followed by a common-source TIA stage. LCDS uses a current-mode receiver compared to a conventional voltage-mode receiver used in most of the signalling technologies such as low-voltage differential signalling, voltage-mode signalling and current-mode logic. The minimum detectable signal level possible with a current-mode receiver for the targeted bit-error rate (BER) makes LCDS an attractive choice. Also the input impedance of the LCDS receiver can be made equal to 100 Ω differential for matching the characteristic impedance of electrical chip-to-chip interconnect. The complete design, analysis and noise characterisation of the TIA front-end is presented. The CGCSTIA is implemented in 1.8 V, 0.18 μm digital CMOS technology. The input-referred noise current and 3-dB bandwidth of the receiver are 1.57 μA and 5.75 GHz, respectively. For the targeted BER of 10^?12, a data transfer rate of 6 Gb/s is achieved, while transmitting the data over a FR4 PCB trace of length 20 cm. The power dissipated in the current-mode receiver is 3.6 mW.     

A low-current Al-gate C-MOS crystal oscillator

The subthreshold properties of MOS transistors have been used advantageously to implement a crystal oscillator that operates at the sub-microampere current levels, using low-voltage metal-gate C-MOS technology. Composed of a reference current generator, a voltage-amplitude regulator, a Pierce oscillator, and an a.c. amplifier, the circuit can be put into a shutdown mode for power conservation.     

Electron-beam fabrication of submicrometer bipolar transistors for high-frequency low-current operation

A submicrometer device technology has been developed for the design and fabrication of bipolar transistors capable of high-frequency operation at low currents. Direct write electron-beam lithography is used with a single-level resist process that is compatible with high dose ion implants and dry etching, and is capable of producing feature sizes to at least the 0.5-µm level. A low temperature local oxidation process is used to minimize parasitic capacitances. Both process and device models are used in the design, which must consider the two-dimensional nature of the base-emitter region, since for these structures, the emitter junction depth is comparable in size to the emitter width. Data are presented and compared on 0.5-, 0.75-, and 1.0-µm devices.     

Design and analysis of pneumatic force generators for mobile robotic systems

Pneumatic components are rather rugged and suitable for harsh environments and therefore are an attractive alternative for mobile robots. Many robotics control algorithms require that the robot actuators be force or torque generators, so the robot controller can impose proper torque levels onto the robot joints as required by the control algorithm. While creating a torque generator using electric actuators is relatively straightforward using current feedback, there are challenges in transforming pneumatic actuators into pure force generators. This paper develops a control algorithm to convert pneumatic actuators into force generators. Because delivered work from a pneumatic actuator is product of the actuator force and the piston's displacement, the actuator force can be effectively controlled through precise measurement of the piston's displacement and robust control of the actuator's work. This paper first develops an exact model of a pneumatic system consisting of a double-acting cylinder and a servo-valve, with the goal of providing an insight into the design and control requirements for pneumatically actuated systems. Using the model, two subjects are presented in detail: 1) derivation of a control algorithm that converts a pneumatic actuator into a force generator for robotics control applications and 2) derivation of equations that can be used to design or size the power source for mobile robotic systems, where continuous source of power is unavailable.     

均匀随机数发生器测试软件包的设计与实现

对随机数发生器进行有效的统计性能测试在离散系统仿真中具有重要意义。从数理统计的角度出发,分析了随机数序列参数检验、均匀性检验和独立性检验的数学基础,并以此为基础运用C＋＋设计了基于动态链接库的随机数发生器统计性能测试软件包。在该测试软件包中,对随机数发生器产生的[0,1]均匀分布随机数序列的参数特性、均匀性和独立性分别从多个方面加以检验,提高了测试的完备性和正确性。最后,通过实例验证了该测试软件包的有效性。     

能改进动圈表头对小电流测量的MOSFET

以前曾经有一个设计实例介绍了用动圈模拟表头测量小于1A电流的十分有趣和有用的方法（参考文献1）。这种设计在表头运转的灵敏度和测量范围选择方面有相当好的灵活性．并且简化了分流电阻器的选择工作。虽然该设计使用了一支双极晶体管来驱动电表，但在某些情况下，MOSFET管会是更好的选择。原始电路中用一个压控电流吸收器来测量双极晶体管的射极电流．而用晶体管的集电极电流驱动模拟表头。双极晶体管的射极和集电极电流（分别是IE和IC）并不相等．原因是射极电流中还包含有基极电流IR。     

可测试低电流电源的简单双恒流载荷

当今的小型家电,如洗碗机、烘干机、电炉等用开关电源代替了体积笨重的线性电源.工程师对这些电流从50mA～1A的电源进行了测试,一般使用电阻或标准现成的电负载.工程师会使用各种大功率电阻来检验多种负载条件以满足合适的设计.多数标准的电负载都是针对平均300W功率的.     

Design and performance of low-current GaAs MMICs forL-band front-end applications

GaAs monolithic microwave integrated circuits (MMICs) with very low current and of very small size have been developed for L-band front-end applications. The MMICs fully employ lumped LC elements with uniplanar configurations. There are two kinds of MMICs: a low-noise amplifier and a mixer. The low-noise amplifier has a noise figure of 2.5 dB and a gain of 11.5 dB. The mixer has a conversion gain of 12.5 dB small local oscillator (LO) power of -3 dBm. Total current dissipation of the two MMICs is less than 8 mA with 3-V drain bias voltages     

纳米光学研究新进展开启了纳机电系统(NEMS)的设计大门

当达到纳米数量级,光在两个非常接近(有时可达到10nm,比光的波长都要小)的表面之间辐射光子会产生能量,在光波长被中断时,光的特性会发生变化,产生出一些不稳定的波,叫做倏逝波(evanescent waves),这些很难预测方向的倏逝波更无法计算,这给研究者带来了巨大的工作挑战.     

Design technique for microwave-transistor power amplifiers

A design technique has been developed which yields the added-power circuit efficiency of a microwave-transistor power amplifier with arbitrary output termination. Good agreement between theory and experiment has been achieved with a 1 W bipolar junction transistor operating at 1.3 GHz.     

Modulo address generators for DSPs

Digital signal processors implement modulo addressing by using separate hardware generation and comparison. To simplify hardware, they restrict the starting address, the displacement value, and/or the buffer length. The authors show that, by rewriting the equations for modulo addressing. It is possible to combine address generation and comparison to simplify hardware without loss in speed     

Transition-matrix construction for pseudorandom binary-sequence generators

A method is described for rapidly finding the elements of a matrix operator which shifts the state of a class of linear sequence generators through a specified time interval. The method is applied to the problem of generating pseudorandom binary sequences with specified time shifts.     

Address generators for linear systolic array

Systolic arrays (SAs) are very efficient architectures for multimedia processing, database management, and scientific computing applications that are characterized by a high number of data access. However, in these data transfer and storage intensive applications, memory access is often the limiting factor to the computation speed. Since the memory subsystem dominates the cost (area), performance and power consumption of the SA, we have to pay a special attention to how memory subsystem can benefit from customization. In this paper we consider memory organization of linear systolic array with bi-directional links (called BLSA) suitable for implementation of broad class of algorithms. We assume that memory is organized into distributed smaller physical memory modules. In order to provide high bandwidth in data access we have designed special hardware, called address generator unit (AGU). The function of AGU is threefold. First, during the initialization, it transforms host address space into BLSA address space. Second, provides efficient memory data access during BLSA operation. Third, performs fast data transfer between BLSA and host at the end of the computation. In this article, we examine the impact on area and performance of memory access related circuity in eliminating computational intensive offset address calculations performed in software by implementing the needed address transformations with the AGUs. By involving hardware AGUs we achieved a speedup of approximately two, compared to the software implementation of address calculation, with a hardware overhead of only 7.6% in the worst case.     

Transistor invertors for low-voltage thermoelectric generators

A transistor invertor is described which gives over 80 % efficiency for a source voltage of 400 mV, as compared with the 44 % recently reported for a tunnel-diode invertor.     

Identifying generators for number theoretic transforms

The author presents results that can be used to obtain all the possible generators for a given number theoretic transform (NTT). A generalisation of the well known Euler theorem is derived which can be used to determine all the generators of a given NTT once the generators over the underlying finite field are identified     

Design technique for MESFET mixers for maximum conversion gain

A design technique for MESFET mixers is described. This technique is based on a mixer analysis program (MIXAN) designed to obtain the value of conversion gain and evaluate the influence of the embedding impedances for any local oscillator power and DC bias, in order to optimized the mixer performance. The MIXAN program, which uses SPICE as a subroutine to determine large-signal current and voltage waveforms, is able to obtain the operating conditions for maximum conversion gain. The good agreement between experimental and simulation results for X-band drain and gate mixers proves the validity of the design technique     

Measurement of the low-current base and emitter resistances of bipolar transistors

A new ac method is proposed to measure the emitter and base resistances of bipolar transistorsat low current levels at which the effective transistor geometry is given by the processing and is unaffected by the changes induced by high currents. The technique is based on a measurement of the input impedance at frequencies below about 50 MHz. It is particularly suited for the measurement of the physical emitter resistance of scaled transistors. The method is illustrated on microwave transistors with metal contacts and on self-aligned digital transistors with polysilicon contacts. A comparison of the results obtained using this method with those from dc methods operating at high currents can be used to explore the current dependencies of the resistances. The technique is applicable both for homojunction and heterojunction transistors.