Constrained parity testing

A generalized testing technique called constrained parity testing is presented for detecting multiple stuck-at faults in any single-output irredundant combinational network by verifying the subparities of the network. Implementation independent testability conditions are established for single- and multiple-input stuck-at faults. A spanning parity signature (SPS) is introduced to detect vacuous faults, which include all the input stuck-at faults and a majority of all other multiple stuck-at faults. The SPS is considered for testing all stuck-at faults in networks with small numbers of fanout lines, and a method of deriving tests for nonvacuous faults is proposed. For networks with large fanouts, a hybrid scheme by combining with syndrome testing is suggested to eliminate or reduce the need for expensive fault simulation. The proposed technique is a theoretical generalization of many existing methods and offers advantages such as versatility, flexibility, low test volume, low test time, high fault coverage, and reduced fault simulation and test generation costs.     

ON SHORTENING TEST SEQUENCE LENGTH FOR SIGNATURE ANALYZER

Based on the built-in self-test for logic circuit, a new approach is proposed to reduce pseudorandom test length. After finding worst faults in the circuit and creating their circuit models the output signals of these models will be compressed by linear feedback shift register. The test length for the worst faults can be obtained by analyzing compressed signature . Finally, using the relation between input probability and test length, we propose a new algorithm to shorten the test sequence length. So the optimum input probability and the shortest test length can be received.     

Security analysis and improvement of two attribute-based signature schemes

In order to overcome the drawbacks of current attribute-based signature (ABS) schemes in terms of security,efficiency and signing policy,Ma,et al.and Cao,et al.respectively proposed a threshold ABS with single attribute au-thority and a multi-authority ABS with signing policy supporting AND,OR,threshold gates,and presented the security proof of their schemes under computational Diffie-Hellman assumption.Both schemes were demonstrated have security pitfalls by presenting specified attacks against them.Specifically,their schemes are all vulnerable to forgery attack.Thus,they are not feasible for practical applications.In addition,the cause of the flaws in these ABS schemes are presented,as well as an improvement of Ma et al.'s scheme.     

A Bist Scheme for Non-Volatile Memories

A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be changed selectively by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location. Either such a signature can be externally compared with the expected one in order to check for the programming operation, or it can be used for comparison purposes when data retention must be self-tested.     

Transparent random access memory testing for pattern sensitive faults

This paper presents a new methodology for RAM testing based on the PS(n, k) fault model (the k out of n pattern sensitive fault model). According to this model the contents of any memory cell which belongs to an n-bit memory block, or the ability to change the contents, is influenced by the contents of any k -1 cells from this block. The proposed methodology is a transparent BIST technique, which can be efficiently combined with on-line error detection. This approach preserves the initial contents of the memory after the test and provides for a high fault coverage for traditional fault and error models, as well as for pattern sensitive faults. This paper includes the investigation of testing approaches based on transparent pseudoexhaustive testing and its approximations by deterministic and pseudorandom circular tests. The proposed methodology can be used for periodic and manufacturing testing and require lower hardware and time overheads than the standard approaches.This work was supported by the NSF under Grant MIP9208487 and NATO under Grant 910411.     

Counter-based compaction: An analysis for BIST

According to some recently published results, counter-based compaction outperforms compaction by linear feedback shift registers. These results, however, are based on oversimplified assumptions. In this paper, we discuss an error model to describe the behavior of a faulty circuit under test. We study the three most popular counter-based compaction schemes, (i.e., one's counting, transition counting and edge counting). Using Markov processes we derive equations for iterative computations of exact aliasing probability for any test session length and determine the asymptotic probability of aliasing. For one's counting, we also present a closed form expression that, for any test session length, gives the exact aliasing probability. Finally, we present some examples to compare the aliasing in the counter-based compaction and compaction by a linear feedback shift register. These examples indicate that aliasing by LFSRs is more predictable than aliasing by counters.     

A structure and technique for pseudorandom-based testing of sequential circuits

Presented is a register structure and generator design which enables non-scan sequential testing using parallel pseudorandom-based patterns applied to the circuit's primary inputs. The proposed register structure and register control strategy uses the circuit under test's (CUT's) natural sequential activity to periodically alter a register's output bias to a value near 0.5 (i.e. alter the spread of 1's in the output stream). Thus, over time, it is possible to introduce a larger spread circuit states than that normally reachable when parallel pseudorandom-based test patterns are applied to the input lines of a CUT. Using the register modification, a simple hardware generation system can be designed and is suitable for both on-chip and external testing. Experiments indicate that high fault coverage is attainable in a relatively short test time.     

高斯-牛顿法在模拟特征分析测试参数优化中的应用

普通的模拟特征分析测试方法直接根据采集的VI曲线进行故障判定,无法自动调整测试参数,测试人员需要手动调整测试参数,这样严重影响测试工作效率。以容性器件为例,根据模拟特征分析原理建立故障前后信号差异的目标函数,依据被测器件参数利用改进的高斯-牛顿迭代法对测试信号进行自动灵敏度调整,计算机仿真结果表明,该方法有效,且优化参数对电流信号差异的提升尤为明显。     

电子产品寿命检测中异常数据的检验

讨论在电子产品的寿命数据中,对同时存在的异常大数据和异常小数据的检验方法,给出了一个明确的判别标准,并以一例说明其应用.     

I DDQ testing as a component of a test suite: The need for several fault coverage metrics

This article is concerned with the role of I _DDQ testing, in conjunction with other types of tests, in achieving high quality. In particular, the argument is made that rather than use a single fault coverage, it is better to obtain a number of different coverages, for different types of faults. To demonstrate the need for increasingly stringent fault coverage requirements, an analysis is given of the relationship between quality, fault coverage and chip area. This analysis shows that as chip area increases, fault coverage must also increase to maintain constant quality levels. Data are then presented from a production part tested with I _DDQ , scan, timing and functional tests. To realistically fault grade I _DDQ tests, three different coverage metrics are considered. The data show differences in tester failures compared to these coverage metrics, depending on whether one uses total I _DDQ failures (parts which fail I _DDQ regardless of whether they fail other tests as well) or unique I _DDQ failures (parts which fail only I _DDQ ). The relative effectiveness of the different components of the full test suite are analyzed and it is demonstrated that no component can be removed without suffering a reduction in quality.     

基于光码柱面的二维地址码相关性分析和码字容量研究

在谱域和时域同时编码的二维OCDMA系统是增加系统容量的主要方案.在一维光码盘和光码环的基础上,设计出直观描述二维λ-t地址码的几何装置-二维光码柱面,直观便捷地描述二维码字结构,给出基于光码柱面的二维码码字相关性分析方法.并根据光码柱面,建立了在光码集本身导出二维码码字容量的分析理论.所得结果与直接引用电通信中的Johnson界得出的结果一致.因此,二维光码柱面给二维的相关性分析和码字容量研究提供了便捷有效的工具.     

A unified approach for fault simulation of linear mixed-signal circuits

The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.This research was supported by the National Science Foundation under grant MIP-9222481.     

On the generation of test patterns for multiple faults

This article presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in FAN and SOCRATES algorithms to guide the search part of the algorithm, and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.     

A new family of 2D variable-weight optical orthogonal codes for OCDMA systems supporting multiple QoS and analysis of its performance

A new family of two-dimensional variable-weight and constant-length optical orthogonal codes (2D VWOOCs) is proposed, and the code cardinality and BER performance for the corresponding OCDMA system are analyzed in this article. It is shown that the cardinality of 2D VWOOC is larger than that of constant-weight 2D OOC and close to the upper bound in theory. In an OCDMA network, the users employing 2D VWOOC codewords with larger Hamming weight outperform the users using 2D VWOOC codewords with smaller Hamming weight in bit-error-rate performance. Therefore, the OCDMA network employing 2D VWOOC can support diverse quality-of-services (QoS) classes and multimedia services, and make the better use of bandwidth resources in optical networks.

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for which on-line testing (OLT) is becoming an essential part in design for testability. In majority of the works on OLT, single stuck at fault model is considered. However in modern integration technology, single stuck at fault model can capture only a small fraction of real defects and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc. are now being considered. In this paper we concentrate on bridging faults for OLT. The reported works on OLT using bridging fault model have considered non-feedback faults only. The basic idea is, as feedback bridging faults may cause oscillations, detecting them on-line using logic testing is difficult. However, not all feedback bridging faults create oscillations and even if some does, there are test patterns for which the fault effect is manifested logically. In this paper it is shown that the number of such cases is not insignificant and discarding them impacts OLT in terms of fault coverage and detection latency. The present work aims at developing an OLT scheme for bridging faults including the feedback bridging faults also, that can be detected using logic test patterns. The proposed scheme is based on Binary Decision Diagrams, which enables it to handle fairly large circuits. Results on ISCAS 89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improves fault coverage, however, increase in area overhead is marginal, compared to schemes only involving non-feedback faults.