拥挤度驱动的总体布线层分配算法

针对多层布线问题，提出以拥挤度为驱动目标，完成布线资源的合理分配，同时达到布线层资源占用少和通孔数少等优化目标的层分配算法．首先采用启发式方法获得初始分配方案，然后通过模拟退火技术优化分配结果，最后采用试探策略优化层资源占用．工业实验数据表明，该算法能够实现线网层合理分配，获得满足拥挤度的优化解．     

一种通孔最小化的三层通道布线算法

本文提出的连通孔最小化的三层通道布线算法,根据线网的接点位置建立线网分层图,并对此图进行三着色,确定出初始布线集和分拆线网集,通过引进线网次序图、压缩空段长度、填充原则和逐步排障法等,将初始布线集和拆网集的线网分配到相应的走线道上.实现线网的互连.本算法已用PASCAL语言编程,并在XT/286机上实现.结果表明,该算法不仅使通孔数大大减少,而且有些例子的走线道数也较一般布线法少.     

一种基于非严格预留层的双层通道布线算法

本文提出一种基于非严格预留层的双层通道布线算法，算法通过确定较好的布线顺序，在基本上不增加空间的情况下，有效地减少GP线与通孔。实验结果证明，该算法能得到较好的布线结果。     

VLSI积木块布图设计的通道划分和总体布线

本文提出了用ＶＬＳＩ积木声布科设计（ＢＢＬ）中的通道划分和总体布线有效算法，通道划分是在角逢数据结构的基础上，对空瓦片进行适当分割和合并，总体布线以通道图和线网排序的为基础，提出了扩张－收缩优化总体布线算法，在保证获得很高布通率的前提下，将线网按最短路径和最少通孔数进行布线，算法已用于Ｃ语言实现，结果令人满意。     

非默认规则线技术下基于多策略的时延驱动层分配算法

层分配作为超大规模集成电路物理设计中的关键环节,在决定布线方案的时延起到非常重要作用.为了优化集成电路的时延性能,现有的层分配工作通常注重优化互连时延和通孔数量,但要么未考虑到对线网中时序关键段的分配问题,要么对线网段的时序关键性的表示不够合理,最终使得算法的时延优化不够理想.为此,本文提出一种非默认规则线技术下基于多策略的时延驱动层分配算法,主要包含4种关键策略:(1)提出轨道数感知的层选择策略,增强层分配器为线网段选择合适布线层的能力;(2)提出多指标驱动的初始线网排序策略,综合考虑线长、信号接收器数和可布线轨道资源等多个指标为线网确定层分配优先级,从而获得高质量的初始层分配结果;(3)提出线网段调整策略,通过重绕线网,将时序关键段调整至上层布线层,优化线网时延;(4)提出线网段时延优化策略,对存在溢出线网进行拆线重绕,从而可同时优化时延和溢出数.实验结果表明,本文提出的算法相比于现有的层分配算法能够在时延和通孔数两个指标上均取得最佳,并且保证不产生溢出.     

一个基于无约束通孔优化的双层布线算法—FOREST

FOREST是一个立足于无约束通孔优化的新的布线算法,它从总体上将布线过程分为拓扑布线和物理布线两部分,并把两者视为相互联系的整体。作为一种启发式算法,它试图综合考虑布通率、布线空间、通孔数和连线总长等因素,算法打破横竖严格分层的限制,并允许不同层线段重叠,FOREST算法适用于一般的通道布线,特别是不规则边界的通道,一些实例的试算表明,FOREST算法具有较好的布线效果,尤其在减少通孔数上,取得了比较满意的结果。     

一种新的与线网顺序无关的随机优化总体布线算法

针对目前总体布线中仍然存在的3个关键问题;布线结果受布线顺序的影响、总体布线图中拥挤区域的不可预见性、线网连接式样受到算法的限制等,该文提出了一种新的不受线网顺序影响的总体布线算法,并实现了相应的总体布线器RINO－Router。该算法采用随机优化方法来保 证先后被拆线重布的线网有相同的通过拥挤区域的机会,并能得到GRG边的拥挤度估计值;采用高效的Steiner树改造算法构造避开拥挤区域的布线树,采用典型电路实例进行了测试,并将布线结果与基于多商品流算法的总体布线器Matula-Router进行了对比。结果表明,RINO－Router能够在短得多的运行时间内求得质量与Matula-Router相近的总体布线解。     

考虑总线时序匹配的多策略层分配算法

在总体布线的过程中,层分配阶段通过控制总线线网的层次影响总线的时序匹配效果.为此,提出考虑总线时序匹配的多策略层分配算法.首先基于线网属性的线网优先级策略,针对线网不同属性的特点得到一个兼顾线长和总线偏差的布线顺序;然后基于贪心策略的初始布线策略,每次布线都对正在布线的线网选择当前最短路径,使相同总线内的线网都尽可能等...     

带有引线端预处理的区域布线算法

提出一种带有引线端优化处理的多层区域布线算法,能处理端点障碍在区域内任意分布的大量布线问题,首先将多端线网划分为二端子线网,并在此基础上根据二端子线网之间的相对位置关系进行分类;然后对每个类型的二端子线网,采用双向迷宫和朝向目标的深度优先搜索策略依次布线;最后通过拆线-重布策略来解决布线冲突．在进行布线搜索之前,对引线端映射到网格点上这一过程引入了一种有效的优化预处理机制,采用二分图中多目标约束寻找最佳匹配的思想和策略来解决引线端优化映射问题．测试并比较了有／无这种优化处理的2种情况,实验结果表明,该算法有效地改善了网格映射的精度和准确性,可缩短线长和提高布通率．     

一种连通孔最小化的通道布线算法

本文根据线网连接端的位置引进了线网位置关系图和线网分层图,从而把连通孔最小化通道布线问题归结为:拆开最少数目的线网使得线网分层图转换成可二着色图。文中导出了通道布线最少连通孔数的公式,并在此基础上提出了一种连通孔最小化通道布线算法。     

Conjugate conflict continuation graphs for multi-layer constrained via minimization

A graph model for describing the relationships among wire segments is crucial to constrained via minimization (CVM) in a VLSI design. In this paper we present a new graph model, called the conjugate conflict continuation graph, for multi-layer CVM with stacked vias. This graph model eases the handling of stacked via problems. An integer linear programming (ILP) formulation and a simulated annealing (SA) algorithm based on this graph model are developed to solve multi-layer CVM. The ILP model is too complicated to solve efficiently. The SA algorithm on average achieves 6.4% via reduction for layouts obtained using a commercial tool under a set of practical constraints in which the metal wires (including pins) used in cell layouts, power rails and rings, and clock routing are treated as obstacles or fixed-layer objects to a multi-layer CVM.     

A gradual neural network approach for FPGA segmented channelrouting problems

A novel neural network approach called gradual neural network (GNN) is presented for segmented channel routing in field programmable gate arrays (FPGA's). FPGA's contain predefined segmented channels for net routing, where adjacent segments in a track can be interconnected through programmable switches for longer segments. The goal of the FPGA segmented channel routing problem, known to be NP-complete, is to find a conflict-free net routing with the minimum routing cost. The GNN for the N-net-M-track problem consists of a neural network of NxM binary neurons and a gradual expansion scheme. The neural network satisfies the constraints of the problem, while the gradual expansion scheme seeks the cost minimization by gradually increasing activated neurons. The energy function and the motion equation are newly defined with heuristic methods. The performance is verified through solving 30 instances, where GNN finds better solutions than existing algorithms within a constant number of iteration steps.     

A parallel genetic algorithm for performance-driven VLSI routing

This paper presents a novel approach to solve the VLSI (very large scale integration) channel and switchbox routing problems. The approach is based on a parallel genetic algorithm (PGA) that runs on a distributed network of workstations. The algorithm optimizes both physical constraints (length of nets, number of vias) and crosstalk (delay due to coupled capacitance). The parallel approach is shown to consistently perform better than a sequential genetic algorithm when applied to these routing problems. An extensive investigation of the parameters of the algorithm yields routing results that are qualitatively better or as good as the best published results. In addition, the algorithm is able to significantly reduce the occurrence of crosstalk     

确定区域详细布线算法

提出了一种确定区域的详细布线算法,它能对不同设计模式进行布线。该算法能适用于任意多层布线情况,并且支持不同布线层具有的不同工艺参数,在构造布线树时,考虑芯片当前的走线拥挤度,使布线比较平均,并加快了算法运行速度、改善了布线质量,在连接两点线网时,构造基于二维迷宫布线结果的分层图,提出了一种对分层图的启发式染色算示来进行布线层分配,大大提高算法布线速度,采用拆线重布的方法来处理布线失败的线网。     

Optimal algorithms for adjacent side routing

We consider the switchbox routing problem of two-terminal nets in the case when all thek nets lie on two adjacent sides of the rectangle. Our routing model is the standard two-layer model. We develop an optimal algorithm that routes all the nets whenever a routing exists. The routing obtained uses the fewest possible number of vias. A more general version of this problem (adjacent staircase) is also optimally solved.