1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

SODEL FET: novel channel and source/drain profile engineering schemes by selective Si epitaxial growth technology

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (C/sub j/) has been reduced in SODEL FET, i.e., C/sub j/ (area) was /spl sim/0.73 fF//spl mu/m/sup 2/ both in SODEL nFET and pFET at Vbias =0.0 V. The body effect coefficient /spl gamma/ is also reduced to less than 0.02 V/sup 1/2/. Nevertheless, current drives of 886 /spl mu/A//spl mu/m (I/sub off/=15 nA//spl mu/m) in nFET and -320 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) in pFET have been achieved in 70-nm gate length SODEL CMOS with |V/sub dd/|=1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond.     

InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.     

An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si/sub 0.5/Ge/sub 0.5/ gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 /spl mu/A//spl mu/m, 8/spl times/10/sup -9/ /spl mu/A//spl mu/m, 87 mV/V, and 95 mV/dec, respectively.     

InGaAs-InP mesa DHBTs with simultaneously high f/sub /spl tau// and f/sub max/ and low C/sub cb//I/sub c/ ratio

We report an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT), fabricated using a conventional triple mesa structure, exhibiting a 370-GHz f/sub /spl tau// and 459-GHz f/sub max/, which is to our knowledge the highest f/sub /spl tau// reported for a mesa InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The collector semiconductor was undercut to reduce the base-collector capacitance, producing a C/sub cb//I/sub c/ ratio of 0.28 ps/V at V/sub cb/=0.5 V. The V/sub BR,CEO/ is 5.6 V and the devices fail thermally only at >18 mW//spl mu/m/sup 2/, allowing dc bias from J/sub e/=4.8 mA//spl mu/m/sup 2/ at V/sub ce/=3.9 V to J/sub e/=12.5 mA//spl mu/m/sup 2/ at V/sub ce/=1.5 V. The device employs a 30 nm carbon-doped InGaAs base with graded base doping, and an InGaAs-InAlAs superlattice grade in the base-collector junction that contributes to a total depleted collector thickness of 150 nm.     

High-responsivity high-gain In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors grown using metal-organic vapor phase epitaxy

We report the growth and fabrication of bound-to-bound In/sub 0.53/Ga/sub 0.47/As-InP quantum-well infrared photodetectors using metal-organic vapor phase epitaxy. These detectors have a peak detection wavelength of 8.5 /spl mu/m. The peak responsivities are extremely large with R/sub pk/=6.9 A/W at bias voltage V/sub b/=3.4 V and temperature T=10 K. These large responsivities arise from large detector gain that was found to be g/sub n/=82 at V/sub b/=3.8 V from dark current noise measurements at T=77 K and g/sub p/=18.4 at V/sub b/=3.4 V from photoresponse data at T=10 K. The background-limited temperature with F/1.2 optics is T/sub BLIP/=65 K for 0相似文献   

50-nm gate Schottky source/drain p-MOSFETs with a SiGe channel

We propose new SiGe channel p-MOSFETs with germano-silicide Schottky source/drains (S/Ds). The Schottky barrier-height (SBH) for SiGe is expected to be low enough to improve the injection of carriers into the SiGe channel and, as a result, current drivability is also expected to improve. In this work, we demonstrate the proposed Schottky S/D p-MOSFETs down to a 50-nm gate-length. The drain current and transconductance are -339 /spl mu/A//spl mu/m and 285 /spl mu/S//spl mu/m at V/sub GS/=V/sub DS/=-1.5 V, respectively. By increasing the Ge content in the SiGe channel from 30% to 35%, the drive current. and transconductance can be improved up to 23% and 18%, respectively. This is partly due to the lower barrier-height for strained Si/sub 0.65/Ge/sub 0.35/ channel than those for strained Si/sub 0.7/Ge/sub 0.3/ channel device and partly due to the lower effective mass of the holes.     

Highly reliable CVD-WSi metal gate electrode for nMOSFETs

In this paper, we first propose an improved chemical vapor deposition (CVD) WSi/sub x/ metal gate suitable for use in nMOSFETs. We studied the relationship between the Si/W ratio of CVD-WSi/sub x/ film and electrical properties of MOSFETs. As a result, it was found that the Si/W ratio strongly affects carrier mobility and the reliability of gate oxide. In the case of higher Si/W ratio, both electron and hole mobility can be improved. For CVD-WSi/sub 3.9/ electrode, electron mobility and hole mobility at 1.2 V of |V/sub g/-V/sub th/| are 331 and 78 cm/sup 2//V/spl middot/s, respectively. These values are almost the same as those for n/sup +/-poly-Si electrode. The improvement of carrier mobility by controlling the Si/W ratio is due to suppression of fluorine contamination in gate oxide. F contamination at the Si/W ratio of 3.9 is found to be less than that at the Si/W ratio of 2.4 from XPS analysis. Workfunction of CVD-WSi/sub 3.9/ gate estimated from C-V measurements is 4.3 eV. In CVD-WSi/sub 3.9/ gate MOSFETs with gate length of 50 nm, a drive current of 636 /spl mu/A//spl mu/m was achieved for off-state leakage current of 35 nA//spl mu/m at power supply voltage of 1.0 V. By using CVD-WSi/sub 3.9/ gate electrode, highly reliable metal gate nMOSFETs can be realized.     

A single-chip CMOS optical microspectrometer with light-to-frequency converter and bus interface

A single-chip CMOS optical microspectrometer containing an array of 16 addressable Fabry-Perot etalons (each one with a different resonance cavity length), photodetectors, and circuits for readout, multiplexing, and driving a serial bus interface has been fabricated in a standard 1.6 /spl mu/m CMOS technology (chip area 3.9 /spl times/ 4.2 mm/sup 2/). The result is a chip that can operate using only four external connections (including V/sub dd/ and V/sub ss/) covering the optical range of 380-500 nm with full-width half-maximum (FWHM) = 18 nm. Frequency output and serial bus interface allow easy multisensor and multichip interfacing using a microcontroller or a personal computer. Power consumption is 1250 /spl mu/W for a clock frequency of 1 MHz.     

A Micropower CMOS-Instrumentation Amplifier

A CMOS switched capacitor instrumentation amplifier is presented. Offset is reduced by an auto-zero technique and effects due to charge injection are attenuated by a special amplifier configuration. The circuit which is realized in a 4-/spl mu/m double poly process has an offset (/spl tau/) of 370 /spl mu/V, an rms input referred integrated noise (0.5 -f/sub c//2) of 79 /spl mu/V, and consumes only 21 /spl mu/W (f/sub c/ = 8 kHz, V/sub DD/ = 3 V).     

A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation

We introduce a novel CMOS transistor fabrication technique using damascene gate with local channel implantation (LCI). This transistor has a benefit to reduce the resistance of source/drain extension (SDE) localizing the severe blanket channel implantation under the channel only. It can reduce the junction capacitance as well. This process technology is reliable for the formation of channel length down to 22 nm with smooth gate line edge roughness. Some unique processes for the small transistor fabrication are also introduced. The 22-nm nMOSFET with 0.9 nm RTO is achieved with the drive current of 930 /spl mu/A//spl mu/m for the off-current of 100 nA//spl mu/m at 1.0 V. Hot carrier reliability exceeding 10 years for 1.0 V operation is also obtained.     

High-power broadly tunable Ho/sup 3+/-doped silica fibre laser

Tuning of the 2.1 /spl mu/m Ho/sup 3+/-doped silica fibre laser is demonstrated for the first time. The /sup 5/I/sub 7//spl rarr//sup 5/I/sub 8/ transition provides tuning over 144 nm, from 2019 to 2163 nm, and a maximum pump-limited output power of 1.58 W at 2100 nm was produced.     

The impact of uniform strain applied via bonding onto plastic substrate on MOSFET performance

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (/spl sim/0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average /spl Delta/I/sub d//I/sub d//spl sim/10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (L/sub g//spl sim/55 nm -0.530 /spl mu/m/W /spl sim/2-20 /spl mu/m). The p-MOSFETs also exhibited I/sub d/-improvement by /spl sim/7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects.     

A resonant tunneling quantum-dot infrared photodetector

A novel device-resonant tunneling quantum-dot infrared photodetector-has been investigated theoretically and experimentally. In this device, the transport of dark current and photocurrent are separated by the incorporation of a double barrier resonant tunnel heterostructure with each quantum-dot layer of the device. The devices with In/sub 0.4/Ga/sub 0.6/As-GaAs quantum dots are grown by molecular beam epitaxy. We have characterized devices designed for /spl sim/6 /spl mu/m response, and the devices also exhibit a strong photoresponse peak at /spl sim/17 /spl mu/m at 300 K due to transitions from the dot excited states. The dark currents in the tunnel devices are almost two orders of magnitude smaller than those in conventional devices. Measured values of J/sub dark/ are 1.6/spl times/10/sup -8/ A/cm/sup 2/ at 80 K and 1.55 A/cm/sup 2/ at 300 K for 1-V applied bias. Measured values of peak responsivity and specific detectivity D/sup */ are 0.063 A/W and 2.4/spl times/10/sup 10/ cm/spl middot/Hz/sup 1/2//W, respectively, under a bias of 2 V, at 80 K for the 6-/spl mu/m response. For the 17-/spl mu/m response, the measured values of peak responsivity and detectivity at 300 K are 0.032 A/W and 8.6/spl times/10/sup 6/ cm/spl middot/Hz/sup 1/2//W under 1 V bias.     

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

Channel width dependence of NMOSFET hot carrier degradation

The channel width dependence of hot carrier reliability on NMOSFETs from 0.4-/spl mu/m to 0.13-/spl mu/m technology has been studied at both I/sub b,peak/ and V/sub g/ = V/sub d/ conditions. Enhanced degradation on narrow width devices happens on most technologies. The I/sub b//I/sub d/ value and vertical electric field are proposed to be the reasons for enhanced degradation on narrow width NMOSFETs.     

Multi-watt, high efficiency, diffraction-limited Nd:YAG planar waveguide laser

An efficient, longitudinally diode-pumped, diffraction-limited, Nd:YAG double-clad planar waveguide laser was operated on four transitions of the Nd/sup 3+/ ion. Optimized output powers of 4.3, 3.5, and 2.7 W were obtained for absorbed pump powers of /spl sim/7 W, for the transitions at the lasing wavelengths of 1.064 /spl mu/m, 946 nm, and 1.3 /spl mu/m, respectively. Operation of the weak /sup 4/F/sub 3/2//spl rarr//sup 4/I/sub 5/2/ transition, lasing at 1.833 /spl mu/m, was demonstrated at an absorbed pump power threshold of 300 mW and an output power of 400 mW, with a nonoptimized output coupling. Diffraction-limited performance was obtained in both the guided and nonguided axes.     

Low-voltage high performance compact all cascode CMOS current mirror

A high performance and compact current mirror with extremely low input and high output resistances (R/sub in//spl sim/0.01/spl Omega/, R/sub out//spl sim/10 G/spl Omega/), high copying accuracy, very low input and output voltage requirements (V/sub in/, V/sub out//spl ges/V/sub DSsat/), high bandwidth (200 MHz using a 0.5 /spl mu/m CMOS technology) and low settling time (25 ns) is proposed. Simulations and experimental results are shown that validate the circuit.