A dynamic threshold voltage MOSFET (DTMOS) for very low voltageoperation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V_dd. On the other hand, V_t is high at V_gs =0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V_dd=0.5 V     

Novel technique for measurement of MOSFET threshold voltage at very low channel currents

A curve tracer reveals a low-level current `spike? in the gate-source characteristic of enhancement-mode MOSFETs. The origin of this spike is explained, and its use in measuring the threshold voltage of any MOSFET at a vanishingly small channel current is described. The technique also identifies whether the MOSFET is n-channel or p-channel, enhancement-mode or depletion-mode.     

Improvement of threshold voltage deviation in damascene metal gatetransistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (ΔV _th) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, ΔV_th of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (ΔV_th) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta₂O₅ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN     

A metal/polysilicon damascene gate technology for RF power LDMOSFETs

This letter describes a metal/polysilicon damascene gate technology for RF power LDMOSFETs. We compare the performance of SOI LDMOSFETs with metal/polysilicon damascene gates to that of identical devices with n/sup +/ polysilicon gates. The gate sheet resistance of the metal/polysilicon gate was 0.2 /spl Omega//sq. This very low sheet resistance greatly improved f/sub max/ and peak PAE, especially for the wide gate fingers that are critical in RF power applications. With a 140 /spl mu/m gate finger width, f/sub max/ was improved from 5 GHz to 25 GHz, and peak PAE at 1.9 GHz was improved from 12% to 52%.     

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V_t) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V_t is high at V_gs=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V_dd=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS)     

Process damage-free damascene metal gate technology for gentle integration of epitaxially grown high-k

This paper presents the first successful attempt to integrate crystalline high-k gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1.9 nm are discussed and compared with devices with rare-earth gate dielectrics fabricated previously in a conventional CMOS process.     

基于红外成像的中低压电网电力稳定器高温运行可靠性图像识别方法

电力稳定器在电网中起到稳定电压的作用,一旦该设备出现异常,电网运输电力质量会受到直接影响。面对这种情况,研究一种基于红外成像技术的中低压电网电力稳定器高温运行可靠性图像识别技术。该研究中利用红外成像技术采集电力稳定器图像并实施预处理。分割电力稳定器红外图像,划分目标区域和背景区域。提取目标区域5个直方图-阶统计特征。以5个直方图-阶统计特征为基础,结合判别系数,构建分类器,实现电力稳定器状态识别。针对存在异常的电力稳定器,计算图像目标区域处的相对温差,确定可靠性等级。结果表明：5个测试稳定器中只有2个稳定器处在异常状态,具体为稳定器2中组成部分3异常,稳定器5中组成部分1异常。稳定器2组成部分3相对温差为82.32%,对应可靠等级为2级,可靠性低;稳定器5组成部分1相对温差为91.35%,对应可靠等级为3级,可靠性非常低。对比实验结果表明,所提方法识别准确率达到92.3%以上,优于对比方法,具有更大的应用价值。     

Influence of sidewall spacer on threshold voltage of MOSFET with high-k gate dielectric

In this paper, an analytical expression of the gate-dielectric fringing-potential distribution is derived for high-k gate-dielectric MOSFET through a conformal-mapping transformation method for the first time. Based on the fringing-potential distribution, the threshold-voltage model of the MOSFET is improved, and the influence of sidewall spacer on the threshold voltage is discussed in detail. Calculated results indicate that low-k sidewall spacer can alleviate the fringing-field effect.     

IDDQ-based diagnosis at very low voltage (VLV) for bridging defects

Bridging defects generate two currents related to the fault-free case: bridge current and downstream current. The latter may complicate the diagnosis of bridging defects. However, in CMOS technologies, the downstream current can be minimised at low power supply (V_DD) values, thus facilitating the diagnosis of such defects. Experimental evidence of this behaviour is presented     

Study of gate leakage mechanism in advanced charge-coupled MOSFET (CC-MOSFET) technology

In this work we present an alternative method to evaluate the ability to charge trap of the thermal silicon oxide grown on n⁺-polysilicon in charge-coupled MOSFET devices. By interpreting the current conduction mechanism through the polysilicon-oxide by Frenkel–Poole model, we were able to evaluate and quantify the amount of charge trapped in it. We propose this approach as a very simple methodology to recognize the properties and quality of insulation of the thermal silicon oxide grown on n⁺-polysilicon devices.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

An analytical model for the threshold voltage of a narrow-width MOSFET

A closed form analytical expression is derived to predict the threshold voltage of a narrow-width MOSFET. The present calculation utilizes the Fourier transform technique to analyze the voltage over the width cross section of the basic MOS device structure. No fitting parameter with experimental data is necessary because the fringe electric field is calculated directly from the relevant physical parameters to deduce the threshold voltage. The dependence of threshold voltage on channel width and substrate bias thus obtained is in reasonable agreement with experimental and numerical results. The effects of field doping and field oxide thickness on the threshold voltage are also taken into consideration. A comparison is made of the present analytical expression for threshold voltage with that, based on an adjustable weighting factor, of earlier analytical models.     

Source electrode evolution of a low voltage power MOSFET under avalanche cycling

This paper presents the impact of high current repetitive avalanche pulses on a low voltage vertical power MOSFET at high temperature. Measurements show that R_DSon decreases with the number of avalanche cycles whereas other electrical parameters stay constant. A simple model proposed in this paper shows that R_DSon measurements are linked to MOSFET source electrode evolution. Also once source electrode has aged standard R_DSon measurements at high current using force and sense are no more representative of silicon on resistance.     

Electrical characterization of crystalline Gd2O3 gate dielectric MOSFETs fabricated by damascene metal gate technology

This paper presents the first successful attempt to integrate crystalline high-K gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness down to 1.9 nm are discussed.     

Analytical 2D modeling for potential distribution and threshold voltage of the short channel fully depleted cylindrical/surrounding gate MOSFET

A two-dimensional analytical model for fully depleted cylindrical/surrounding gate MOSFET is presented. We used the evanescent mode analysis to solve the 2D Poisson's equation and to deduce analytically the surface potential and threshold voltage expressions of this device. Comparison with the other models reveals a good agreement.     

An analytical expression for the threshold voltage of a small geometry MOSFET

A closed form analytical expression for the threshold voltage of a small geometry MOSFET is developed. The threshold voltage expression is derived from a three dimensional geometrical approximation of the bulk charge. The threshold voltage is expressed as a function of gate oxide thickness, channel doping concentraton, junction-depth, backgate bias and channel length and width. The theory is compared with experimental results and the agreement is close.     

Impacts of gate electrode materials on threshold voltage (V/sub th/) instability in nMOS HfO/sub 2/ gate stacks under DC and AC stressing

Ultrathin nMOSFET hafnium oxide (HfO/sub 2/) gate stacks with TiN metal gate and poly-Si gate electrodes are compared to study the impact of the gate electrode on long term threshold instability reliability for both dc and ac stress conditions. The poly-Si/high-/spl kappa/ interface exhibits more traps due to interfacial reaction than the TiN/high-/spl kappa/ interface, resulting in significantly worse dc V/sub th/ instability. However, the V/sub th/ instability difference between these two stacks decreases and eventually diminishes as ac stress frequency increases, which suggests the top interface plays a minor role in charge trapping at high operating frequency. In addition, ac stress induced interface states (Nit) can be effectively recovered, resulting in negligible G/sub m/ degradation.     

Source-to-drain nonuniformly doped channel (NUDC) MOSFET structuresfor high current drivability and threshold voltage controllability

The source-to-drain nonuniformly doped channel (NUDC) MOSFET has been investigated to improve the aggravation of the V_th lowering characteristics and to prevent the degradation of the current drivability. The basic concept is to change the impurity ions to control the threshold voltage, which are doped uniformly along the channel in the conventional channel MOSFET, to a nonuniform profile of concentration. The MOSFET was fabricated by using the oblique rotating ion implantation technique. As a result, the V_th lowering at 0.4-μm gate length of the NUDC MOSFET is drastically suppressed both in the linear region and in the saturation region as compared with that of the conventional channel MOSFET. Also, the maximum carrier mobility at 0.4-μm gate length is improved by about 20.0%. Furthermore, the drain current is increased by about 20.0% at 0.4-μm gate length     

A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSItechnology

A novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated. It is shown that by adding a layer of material with a larger workfunction to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability. The threshold voltage roll-off can be compensated and tuned by controlling the length of this second gate. The new structure has great potential in breaking the barrier of deep-suhmicron MOSFET's scaling beyond 0.1 μm technologies     

A novel low-voltage N-channel heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) with p-type doped SiGe body

A novel N-channel Si/SiGe heterostructure dynamic threshold voltage MOSFET (N-HDTMOS) has been proposed and fabricated. The Si/SiGe N-HDTMOS consists of an unstrained surface Si channel and heavily p-type doped SiGe body. The potential of the conduction band edge of the surface Si channel can be lowered by introducing a heavily p-type doped SiGe layer into a suitable position in the body region. As a result, the N-HDTMOS shows a threshold voltage reduction and a body effect factor (/spl gamma/) enhancement while keeping high doping concentration in the SiGe layer. The fabricated SiGe N-HDTMOS exhibits superior properties, that is, 0.1 V reduction of V/sub th/, 1.5 times enhancement of /spl gamma/, and 1.3 times saturated current, as compared with those of Si N-DTMOS.