锗纳米线的性能与应用

重点分析讨论了锗纳米线在电学、光学、光电导等特性及其在场效应晶体管制造方面的研究应用现状与最新进展。综合分析表明,未经处理的锗纳米线表面存在一层氧化物及缺陷,与电极连接时欧姆接触性能较差,在制备锗纳米线器件以前必须对锗纳米线表面进行钝化以便沉积电极;对锗纳米线进行掺杂可以改善Ge纳米线的性能,制造出实用Ge纳米线器件。指出在一根纳米线上生长硅/锗半导体纳米线形成硅/锗半导体界面,直接用单根纳米线制造具有完整功能的电子器件是将来重要的研究方向。     

锗纳米线的性能与应用

重点分析讨论了锗纳米线在电学、光学、光电导等特性及其在场效应晶体管制造方面的研究应用现状与最新进展。综合分析表明,未经处理的锗纳米线表面存在一层氧化物及缺陷,与电极连接时欧姆接触性能较差,在制备锗纳米线器件以前必须对锗纳米线表面进行钝化以便沉积电极;对锗纳米线进行掺杂可以改善Ge纳米线的性能,制造出实用Ge纳米线器件。指出在一根纳米线上生长硅/锗半导体纳米线形成硅/锗半导体界面,直接用单根纳米线制造具有完整功能的电子器件是将来重要的研究方向。     

金属/氮化物肖特基势垒和欧姆接触研究进展

金属 /氮化物肖特基势垒和欧姆接触是蓝紫光光学器件及高温大功率电子器件中的关键工艺。氮化物半导体是一种极性材料 ,表面态密度较低 ,费米能级钉扎效应较弱 ,表面处理能显著影响接触特性。样品表面的沾污和氧化层也会使接触特性显著退化。宽禁带材料的杂质离化能高 ,重掺杂比较困难。深能级陷阱对载流子的俘获效应很强。这些因素都增加了接触的制作难度 ,促使人们寻求新的方案来改进接触特性。文中从金属 /半导体接触的物理模型出发来综述肖特基势垒和欧姆接触的研究进展 ,希望能给器件研究者提供新的思路。     

UV/Ozone 表面处理对AlGaN/GaN HEMTs 性能的影响

工艺过程中对晶圆表面处理对制作出高性能的AlGaN/GaN HEMT起到至关重要的作用,洁净的表面能够有效提高器件性能以及器件可靠性。本文发现通过UV/Ozone表面处理,AlGaN/GaN HEMT器件的欧姆接触以及肖特基接触的电学特性均发生明显变化,根据实验中现象以及相关实验数据,并且采用X射线光电子能谱对实验样品进行表面分析测试,着重阐述了UV/Ozone处理对晶圆表面的作用,以及其影响AlGaN/GaN HEMT器件欧姆接触特性以及肖特基接触特性的原因。     

AlGaN器件欧姆接触的研究进展

作为制备光电子器件例如紫外光子探测器、异质结场效应晶体管(HFET)、高电子迁移率晶体管(HEMT)异质结场效应管等的一种宽禁带半导体材料, III V 族氮化物AlGaN器件近年来颇受关注.AlGaN与金属之间的低阻欧姆接触的实现问题阻碍了AlGaN(基)器件的发展.通过对相关文献的归纳分析,介绍了近年来AlGaN器件在欧姆接触形成、金属化方案、合金化工艺及表面处理等方面的研究进展.     

p型GaN基器件的欧姆接触

宽带隙的GaN具有优良的物理和化学性质,己成为半导体领域研究的热点之一。p型GaN的欧姆接触问题制约了GaN基器件的进-步发展。本文首先介绍了欧姆接触的原理及评价方法,详细讨论了实现良好的p型GaN欧姆接触的主要方法是采取表面处理技术、选择合适的金属电极材料和进行热退火处理,以及研究进展情况。最后指出目前存在的问题并提出今后的研究方向。     

硅纳米线的掺杂工艺与检测

掺杂硅纳米线有可能成为一种重要的硅纳米电子器件材料。因而,硅纳米线的掺杂工艺与检测很重要。半导体的掺杂工艺主要为扩散法,而硅纳米半导体线的掺杂检测方法主要包括电流-电压法、拉曼光谱、光致发光(PL)光谱、X-射线光电子能谱(XPS)及近边X-射线吸收精细结构光谱(NEXAFS)等。该文介绍了可引入到硅纳米线研究的现有半导体的掺杂工艺及检测方法,并就硅纳米线的掺杂工艺及检测的最新进展做作了详细的讨论。     

表面处理对Au-CdZnTe电极接触性能的影响

碲锌镉(CdZnTe)是制备X射线、(y)射线探测器的一种理想半导体材料.CdZnTe欧姆接触电极是制备CdZnTe核辐射探测器的关键技术之一.表面加工状态是影响欧姆接触性能的重要因素,文中研究了4种表面处理工艺对Au-CdZnTe电极接触性能的影响.研究发现对晶片表面进行溴甲醇腐蚀处理和机械化学抛光均有助于提升Au-CdZnTe电极欧姆接触性能.对晶片进行机械化学抛光后再进行溴甲醇腐蚀处理,使用这种晶片所制备的电极具有更加优良的综合电学性能.     

提高硅纳米墙光电器件背部欧姆接触的超声修饰方法

提供了一种硅纳米墙结构器件的背面电极接触改善方法。通过利用超声的方法修饰金属催化法制备的硅纳米墙结构,并制备了AZO／硅纳米墙异质结光电器件。研究发现超声波可以对金属催化法制备的纳米硅墙进行单面修饰,与未经超声修饰的样品制备的器件相比,超声修饰能够改善硅纳米墙器件的背面电极欧姆接触,2 min的超声修饰可以将器件的串联电阻从587 Ω下降到082 Ω,填充因子提高86％,光电转换效率提高762％,提高了光电器件的载流子收集效率。     

金属援助硅化学刻蚀法可控制备硅纳米线阵列

基于金属援助硅化学刻蚀机理,成功地发展了一种形貌可控地制备硅纳米线阵列的有效方法。在该方法中,通过银纳米颗粒催化层的微结构和硅化学刻蚀的时间来调控硅纳米线阵列的形貌。扫描电子显微镜(SEM)形貌表征的实验结果证实:硅纳米线阵列的孔隙率依赖银纳米颗粒催化层的微结构,硅纳米线阵列的高度依赖于硅的刻蚀时间。这种形貌可控地制备单晶硅纳米线阵列的方法简单、有效,可用于构筑硅纳米线光伏电池等各种硅基纳米电子器件。     

Effect of alkali treatment on the spectral response of silicon-nanowire solar cells

The effect of alkali treatment of Si nanowires (SiNWs) on the spectral response of solar cells was investigated using monochromatic incident photon-to-electron conversion efficiency spectroscopy. SiNWs were prepared on a substrate by metal-assisted etching and were then treated with NaOH/isopropanol. The results show that alkali treatment of SiNWs for 30 s obviously improved the cell conversion efficiency. This was attributed to enhancement of the red light response and a decrease in surface reflectivity from 6% to ~2%. However, SiNW alkali treatment led to poor blue light response, which is a major limiting factor for efficient SiNW solar cells. To improve the photovoltaic properties of SiNW cells, a near-complete response over the whole solar spectrum is essential.     

Improving the performance of radial n-i-p junction Si nanowire solar cells by catalyst residue removal

It is hoped that silicon nanowire (SiNW)-based solar cells will provide the basis for a new generation of photovoltaics. However, metal-catalyzed SiNWs contain metal residues (such as indium) which may degrade the performance of solar cells. In this study, we prepared SiNW solar cells by plasma-enhanced chemical vapor deposition using indium as the catalyst to grow the SiNWs. The SiNWs were treated with hydrochloric acid to reduce the indium contamination at different concentrations, C_HCl (1–5%). We found the decreasing the indium contamination improved the performance of the solar cells at optimum C_opHCl. However, the performance of the solar cells decreased when C_HCl exceeded C_opHCl. This was attributed to the variation in the conduction-band offset ΔE_c between the n type amorphous silicon layer (E_c n-a-Si) and the n type crystalline silicon nanowires (E_c n-c-SiNWs). Finally, a conversion efficiency (Eff) improvement from 2.11% to 6.18% was obtained with the optimized C_HCl.     

In‐Plane Self‐Turning and Twin Dynamics Renders Large Stretchability to Mono‐Like Zigzag Silicon Nanowire Springs

Crystalline Si nanowire (SiNW) springs, produced via a low temperature (<350 °C) thin film technology, are ideal building blocks for stretchable electronics. Herein, a novel cyclic crystallographic‐index‐lowering self‐turning and twin dynamics is reported, during a tin‐catalyzed in‐plane growth of SiNWs, which results in a periodic zigzag SiNW without any external parametric intervention. More interestingly, a unique twin‐reflected interlaced crystal‐domain structure has been identified for the first time, while in situ and real‐time scanning electron microscopy observations reveal a new twin‐triggering growth mechanism that is the key to reset a complete zigzag growth cycle. Direct “stress–strain” testing of the SiNW springs demonstrates a large stretchability of 12% under tensile loading, indicating a whole new strategy and capability to engineer mono‐like SiNW channels for high performance stretchable electronics.     

Heterojunction based hybrid silicon nanowire solar cell: surface termination,photoelectron and photoemission spectroscopy study

Silicon nanowires (SiNWs) combined with a conducting polymer are studied to constitute a hybrid organic/inorganic solar cell. This type of cell shows a particularly high interfacial area between SiNWs and the polymer so that interfacial control and interface optimization are required. For that purpose, we terminated the SiNW surfaces with well selected functional groups (molecules) such as native oxide (hereinafter SiO₂‐SiNW), hydrogen (hereinafter H‐SiNW) and methyl (hereinafter CH₃‐SiNW). A radial hetero‐junction solar cell is formed, and the cell parameters with and without interface control by functionalization with molecules are compared. Electronically, the three surfaces were close to flat‐band conditions. The CH₃‐SiNW, H‐SiNW and SiO₂‐SiNW produced a surface dipole of −0.12, +0.07 and 0.2 eV and band bending of 50, 100 and 170 meV, respectively. The surface properties of functionalized SiNWs are investigated by photoelectron yield (PY) and photoemission spectroscopy. PY studies on functionalized SiNWs are presented for the first time, and our results show that this type of measurement is an excellent option to carry out interface optimization of NWs for envisaged nano‐electronic and photonic applications. The solar cell efficiency is increased dramatically after terminating the surface with CH₃ molecules due to the decrease of the defect emission. The differently functionalized SiNW surfaces showed identical absorbance, reflectance and transmission so that a change in PY can be attributed to the Si–C bonds at the surface. This finding permits the design of new solar cell concepts. Copyright © 2013 John Wiley & Sons, Ltd.     

Surface‐Dominated Transport Properties of Silicon Nanowires

Surface effects are widely recognized to significantly influence the properties of nanostructures, although the detailed mechanisms are rarely studied and unclear. Herein we report for the first time a quantitative evaluation of the surface‐related contributions to transport properties in nanostructures by using Si nanowires (NWs) as a paradigm. Critical to this study is the capability of synthesizing SiNWs with predetermined conduction type and carrier concentration from Si wafer of known properties using the recently developed metal‐catalyzed chemical etching method. Strikingly, the conductance of p‐type SiNWs is substantively larger in air than that of the original wafer, is sensitive to humidity and volatile gases, and thinner wires show higher conductivity. Further, SiNW‐based field‐effect transistors (FETs) show NWs to have a hole concentration two orders of magnitude higher than the original wafer. In vacuum, the conductivity of SiNWs dramatically decreases, whereas hole mobility increases. The device performances are further improved by embedding SiNW FETs in 250 nm SiO₂, which insulates the devices from atmosphere and passivates the surface defects of NWs. Owing to the strong surface effects, n‐type SiNWs even change to exhibit p‐type characteristics. The totality of the results provides definitive confirmation that the electrical characteristics of SiNWs are dominated by surface states. A model based on surface band bending and carrier scattering caused by surface states is proposed to interpret experimental results. The phenomenon of surface‐dependent transport properties should be generic to all nanoscale structures, and is significant for nanodevice design for sensor and electronic applications.     

Engineering in-plane silicon nanowire springs for highly stretchable electronics

Crystalline silicon (c-Si) is unambiguously the most important semiconductor that underpins the development of modem microelectronics and optoelectronics,though the rigid and brittle nature of bulk c-Si makes it difficult to implement directly for stretchable applications.Fortunately,the one-dimensional (1 D) geometry,or the line-shape,of Si nanowire (SiNW) can be engineered into elastic springs,which indicates an exciting opportunity to fabricate highly stretchable 1D c-Si channels.The implementation of such line-shape-engineering strategy demands both a tiny diameter of the SiNWs,in order to accommodate the strains under large stretching,and a precise growth location,orientation and path control to facilitate device integration.In this review,we will first introduce the recent progresses of an in-plane self-assembly growth of SiNW springs,via a new in-plane solid-liquidsolid (IPSLS) mechanism,where mono-like but elastic SiNW springs are produced by surface-running metal droplets that absorb amorphous Si thin film as precursor.Then,the critical growth control and engineering parameters,the mechanical properties of the SiNW springs and the prospects of developing c-Si based stretchable electronics,will be addressed.This efficient line-shape-engineering strategy of SiNW springs,accomplished via a low temperature batch-manufacturing,holds a strong promise to extend the legend of modem Si technology into the emerging stretchable electronic applications,where the high carrier mobility,excellent stability and established doping and passivation controls of c-Si can be well inherited.     

Hierarchically Ordered Arrays of Noncircular Silicon Nanowires Featured by Holographic Lithography Toward a High‐Fidelity Sensing Platform

A novel, highly uniform and tunable hybrid plasmonic array is created via ion‐milling, catalytic wet‐etching and electron‐beam evaporation, using a holographically featured structure as a milling mask. A simple and low‐cost prism holographic lithography (HL) technique is applied to create an unprecedentedly coordinated array of elliptic gold (Au) holes, which act as the silicon (Si) etching catalyst in the reaction solution used to fabricate an elliptic silicon nanowire (SiNW) array; here, the SiNWs are arrayed hierarchically in such a way that three SiNWs are triangularly coordinated, and the triangles are arranged hexagonally. After removing the polymeric mask and metal thin film, the highly anisotropic thick Au film is deposited on the SiNW arrays. This hybrid substrate shows tunable optical properties in the near‐infrared (NIR) region from 875 nm to 1030 nm and surface‐enhanced Raman scattering (SERS) activities; these characteristics depend on the catalytic wet etching time, which changes the size of the vertical gap between the Au thick films deposited separately on the SiNWs. In addition, lateral interparticle coupling induces highly intensified SERS signals with good homogeneity. Finally, the Au‐capped elliptical SiNW arrays can be hierarchically patterned by combining prism HL and conventional photolithography, and the highly enhanced fluorescence intensity associated with both the structural effects and the plasmon resonances is investigated.     

表面钝化硅纳米线的能带结构

采用第一性原理的方法计算了不同尺寸的(100)硅纳米线在H饱和及F饱和下的电子结构.计算结果表明,F饱和与H饱和的(100)硅纳米线均为直接禁带半导体,但F饱和硅纳米线的禁带宽度和价带有效质量都远小于H饱和硅纳米线,这一现象可用价带顶的σ-n杂化效应来解释.计算结果还表明,H或F饱和的(100)硅纳米线的极限--硅单原子链则表现为间接带隙半导体,文中对这一现象进行了分析和讨论.     

Top-Down Silicon Nanowire-Based Thermoelectric Generator: Design and Characterization

A silicon nanowire (SiNW) array-based thermoelectric generator (TEG) was assembled and characterized. The SiNW array had pitch of 400?nm, and SiNW diameter and height of <100?nm and ~1???m, respectively. The SiNW array was formed using a top-down approach: deep-ultraviolet (UV) lithography and dry reactive-ion etching. Specific groups of SiNWs were doped n- and p-type using ion implantation, and air gaps between the SiNWs were filled with silicon dioxide (SiO₂). The bottom and top electrodes were formed using a nickel silicidation process and aluminum metallization, respectively. Temperature difference across the TEG was generated with a heater and a commercial Peltier cooler. A maximum open-circuit voltage of 2.7?mV was measured for a temperature difference of 95?K across the whole experimental setup, corresponding to power output of 4.6?nW. For further improvement, we proposed the use of polyimide as a filler material to replace SiO₂. Polyimide, with a rated thermal conductivity value one order of magnitude lower than that of SiO₂, resulted in a larger measured thermal resistance when used as a filler material in a SiNW array. This advantage may be instrumental in future performance improvement of SiNW TEGs.     

基于高温热处理的InSb晶片性能研究

近年来,为了满足新一代百万像元、高集成度、高性能红外焦平面探测器的发展需求,人们对高晶格质量、高表面状态InSb晶片的要求越来越高.为了提高用生长态晶体加工的InSb晶片的性能,对晶片高温热处理进行了研究.通过采用特殊设计的晶片承载装置并结合相应的晶片热处理配合方法,优化了晶体生长态遗传的固有缺陷以及由晶片加工过程引入...