Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays

An analytical design methodology for continuous-time (CT) bandpass (BP) /spl Sigma//spl Delta/ modulators is presented. Second- and fourth-order tunable continuous time BP /spl Sigma//spl Delta/ modulator design equations are presented. A novel /spl Sigma//spl Delta/ loop architecture, where the traditional CT BP loop filter function is replaced with the filter function with fractional delays, is proposed. Validity of the methodology is confirmed by mixed-signal behavioral simulations.     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.     

Continuous-time /spl Delta//spl Sigma/ modulators using distributed resonators

We derive a method for using distributed resonators in /spl Delta//spl Sigma/ modulators and demonstrate these /spl Delta//spl Sigma/ modulators have several advantages over existing /spl Delta//spl Sigma/ modulator architectures. Like continuous-time (CT) /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators do not require a high-precision track-and-hold, and additionally can take advantage of the high-Q of distributed resonators. Like discrete-time /spl Delta//spl Sigma/ modulators, the proposed /spl Delta//spl Sigma/ modulators are relatively insensitive to feedback loop delays and can subsample. We present simulations of several types of these /spl Delta//spl Sigma/ modulators and examine the challenges in their design.     

Hexagonal /spl Sigma//spl Delta/ modulators in power electronics

Design techniques for /spl Sigma//spl Delta/ modulators from communications are applied and adapted to improve the spectral characteristics of high frequency power electronic applications. A high frequency power electronic circuit can be regarded as a quantizer in an interpolative /spl Sigma//spl Delta/ modulator. We review one dimensional /spl Sigma//spl Delta/ modulators and then generalize to the hexagonal sigma-delta modulators that are appropriate to three-phase converters. A range of interpolative modulator designs from communications can then be generalized and applied to power electronic circuits. White noise spectral analysis of sigma-delta modulators is generalized and applied to analyze the designs so that the noise can be shaped to design requirements. Simulation results for an inverter show significant improvements in spectral performance.     

Hybrid /spl Sigma//spl Delta/ modulators with adaptive calibration

This paper describes an architecture for stable high-order /spl Sigma//spl Delta/ modulation. The architecture is based on a hybrid /spl Sigma//spl Delta/ modulator, wherein hybrid integrators replace conventional analog integrators. The hybrid integrator, which is a combination of an analog integrator and a digital integrator, offers an increased dynamic range and helps make the resulting high-order /spl Sigma//spl Delta/ modulator stable. However, the hybrid /spl Sigma//spl Delta/ modulator relies on precise matching of analog and digital paths. In this paper, a calibration technique to alleviate possible mismatch between analog and digital paths is proposed. The calibration adaptively adjusts the digital integrators so that their transfer functions match the transfer functions of corresponding analog integrators. Through behavioral-level simulations of fourth-order /spl Sigma//spl Delta/ modulators, the calibration technique is verified.     

IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator for digital receiver applications

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allow direct sampling of an IF signal, reducing analog hardware, and make it easier to realize completely software-programmable receivers. This paper presents the circuit design of and test results from a continuous-time tunable IF-sampling fourth-order bandpass /spl Delta//spl Sigma/ modulator implemented in InP HBT IC technology for use in a multimode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs-GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The fourth-order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wide-band and narrow-band operation. The IF is tunable from 140 to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5-V power supplies, the fabricated fourth-order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal-to-(noise + distortion) ratio (SNDR) of 78 dB at 1 MHz BW and 50 dB at 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB at 1 MHz BW and 47.7 dB at 60 MHz BW.     

Improved design method for continuous-time quadrature bandpass /spl Sigma//spl Delta/ ADCs

In continuous-time quadrature bandpass /spl Sigma//spl Delta/ ADCs it is desirable to limit the number of cross-couplings. This can be achieved by implementing the loop as a cascade of complex integrators with only real coefficients. It is shown that this may result in a very poor approximation of the desired noise transfer function, because the effect of the DAC pulse is not taken into account correctly. A simple implementation that solves this problem is proposed.     

A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture

In this paper, we present a new continuous-time bandpass delta-sigma (/spl Delta//spl Sigma/) modulator architecture with mixer inside the feedback loop. The proposed bandpass /spl Delta//spl Sigma/ modulator is insensitive to time-delay jitter in the digital-to-analog conversion feedback pulse, unlike conventional continuous-time bandpass /spl Delta//spl Sigma/ modulators. The sampling frequency of the proposed /spl Delta//spl Sigma/ modulator can be less than the center frequency of the input narrow-band signal.     

A fast block-based nonlinear decoding algorithm for /spl Sigma//spl Delta/ modulators

Previous work has established that the digital output of a /spl Sigma//spl Delta/ modulator as an A/D converter contains more information about the analog input than is extracted with conventional linear filtering. Under reasonable mathematical assumptions, optimal nonlinear decoding of the digital output can achieve significantly larger signal-to-noise ratios than linear filtering. However, the hitherto proposed decoding algorithms only demonstrate conceptual feasibility and are impractical from a computational point of view. We present a new block-based decoding algorithm that, like previous work, employs projections onto convex sets. The algorithm owes its speed to a change of projection norm, an accelerated convergence scheme, and a decimation-like subsampling; it is on the order of 10/sup 4/-10/sup 5/ times faster than one previously published algorithm for typical parameter values, and about 2-10 times slower than linear decoding. The new algorithm is applicable to all currently popular /spl Sigma//spl Delta/ architectures.<>     

A 1-V 10.7-MHz fourth-order bandpass /spl Delta//spl Sigma/ modulators using two switched op amps

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-/spl mu/m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.     

High-level synthesis of switched-capacitor, switched-current and continuous-time /spl Sigma//spl Delta/ modulators using SIMULINK-based time-domain behavioral models

This paper presents a high-level synthesis tool for /spl Sigma//spl Delta/ modulators (/spl Sigma//spl Delta/Ms) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for /spl Sigma//spl Delta/M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of /spl Sigma//spl Delta/Ms using both discrete-time and continuous-time circuit techniques.     

A vertically integrated tool for automated design of /spl Sigma//spl Delta/ modulators

We present a tool that starting from high-level specifications of switched-capacitor (SC) /spl Sigma//spl Delta/ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design and innovative heuristics for increased computer efficiency as compared with conventional statistical optimization. The tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced /spl Sigma//spl Delta/ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: (1) a 16 b @ 16 kHz output rate second-order /spl Sigma//spl Delta/ modulator; and (2) a 17 b @ 40 kHz output rate fourth-order /spl Sigma//spl Delta/ modulator. Both use SC fully differential circuits and were designed using the proposed tool and manufactured in a 1.2 /spl mu/m CMOS double-metal double-poly technology.<>     

Quadrature /spl Sigma//spl Delta/ modulators with a dynamic element matching scheme

This paper presents a new topology of a multibit quadrature bandpass sigma-delta modulator which employs a simple dynamic element matching (DEM) technique in order to reduce the effects of path mismatch, namely aliasing in the signal band of the mirror images of the signal and of the quantization noise. The DEM scheme results in a reduction of the aliasing of the quantization noise mirror image while it reduces the input signal mirror image alias problem to a self-image problem. It is shown that the self-image can be completely removed in switched-capacitor implementations by using the same capacitors to sample the input and the reference of the feedback digital-analog converters (DACs). Moreover, a simple method for extending low-pass mismatch noise shaping techniques to the complex bandpass case is proposed for the case of multibit feedback DACs.     

Noise-coupled /spl Delta//spl Sigma/ ADC's

The first-order noise coupling scheme proposed earlier is generalised to the realisation of higher-order enhancement. It is also extended to single-stage DeltaSigma loops, and to split structures with self-enhancement. The advantages and limitations of these new DeltaSigma architectures are compared with those of conventional single-stage and cascade DeltaSigma structures. As demonstrated by an example, they exhibit improved stability and robustness under practical fabrication conditions     

Interstage network to control overload in cascaded continuous-time /spl Sigma//spl Delta/ modulators

An improved interstage network suitable for avoiding overload and for increasing the signal-to-noise ratio in low-oversampling-ratio cascaded continuous-time SigmaDelta modulators is reported. Feedforward coefficients, going from the input signal to the second stage, are used to control overload without affecting the behaviour of the noise cancellation filters. Moreover, the anti-aliasing functionality is preserved. Simulation results show the utility of the proposed network in terms of the overload performance     

Sturdy MASH /spl Delta//spl Sigma/ modulator

A new Delta-Sigma modulator is proposed. Its operation is similar to that of a multi-stage noise-shaping structure but requires no digital noise cancellation filters. Thus, the need for matching required between analogue and digital filters is eliminated. Simulation results and mathematical analysis demonstrate the effectiveness of this structure     

Design of low-voltage MOSFET-only /spl Sigma//spl Delta/ modulators in standard digital CMOS technology

A design strategy of low-voltage high-linearity MOSFET-only /spl Sigma//spl Delta/ modulators in standard digital CMOS technology is presented. The modulators use substrate-biased MOSFETs in the depletion region as capacitors, linearized by different compensation techniques. This work shows the design, simulation and measured results of a number of MOSFET-only /spl Sigma//spl Delta/ modulators using different implementations of so called compensated depletion-mode MOS capacitors. The modulators are designed for the demands of speech band applications. The performance of the modulators proves the capability of compensated depletion-mode MOS capacitors to fulfill analog circuit requirements at low supply voltages with reduced processing efforts.     

Nonlinearity correction for multibit /spl Delta//spl Sigma/ DACs

This paper presents a digital correction technique for wide-band multibit error-feedback (EF) digital-to-analog converters (DACs). The integral nonlinearity (INL) error of the multibit DAC is estimated (on line or off line) by a calibration analog-to-digital converter (CADC) and stored in a random-access memory table. The INL values are then used to compensate for the multibit DAC's distortion by a simple digital addition. The accuracy requirements for the error estimates are derived. These requirements can be significantly relaxed when the correction is combined with data-weighted averaging (DWA). Simulation and discrete-component measurement results are presented for a fourth-order 5-bit EF DAC. The results show a 14-bit DAC operating at an oversampling ratio of 8, which is suitable for digital subscriber line applications. The correction uses simple digital circuitry and a 3-bit CADC enhanced by DWA.