高效率低谐波失真宽带功率放大器设计

基于连续型功率放大器理论,提出一种高效低谐波失真宽带功率放大器的设计方法,并采用GaN高电子迁移率晶体管(HEMT)器件设计了验证电路。结合连续型功率放大器理论和多谐波双向牵引技术,找到一簇最佳负载阻抗值,并运用切比雪夫低通滤波器形式的阻抗变换器设计宽带匹配网络。偏置电路采用双扇形开路微带线和滤波电路相结合的方法进行设计,以减小电路尺寸和扩展具有高输入阻抗偏置电路的带宽。实验结果表明,在1.7~2.7 GHz工作频带内,功率附加效率为50%~60%,输出功率大于4 W,增益为(14±0.9)dB,二次谐波失真小于-25 dBc,三次谐波失真小于-60 dBc。     

宽带F 类功率放大器的设计

提出了一款4G 频段全覆盖高输出功率高效率功率放大器。设计采用的是Cree 公司提供的GaN HEMT 晶体管CGH40025F。基于F 类功率放大器的设计理论,通过对晶体管的输入输出端均采用谐波控制网络,并将渐变式阻抗匹配这种宽带匹配方法应用到输入输出端的基波匹配当中。在实现二次谐波阻抗匹配至低阻抗区,三次谐波阻抗匹配至高阻抗区的同时基波阻抗被匹配至50Ω附近,从而有效提高了功率放大器的输出功率、效率和带宽。最终的测试结果表明在1. 7 ~ 2. 7 GHz 频率范围内,漏极效率维持在62. 55% ~ 76%,输出功率在20 ~ 41W,增益在10 dB 以上。仿真与实测结果基本一致。     

基于GaN器件的连续型高效宽带功率放大器设计*

提出一种高效宽带功率放大器的设计方法,并基于GaN HEMT 器件CGH40010F 设计了验证电路。利用功放管输出寄生参数的等效网络,将基于连续型功放理论得到的负载阻抗转换到封装参考面上,并利用多谐波双向牵引技术对转换后的负载阻抗进行适当调整,使二次谐波负载阻抗位于高效率区以及基频负载阻抗能够获得高功率附加效率和高输出功率。谐波阻抗位于高效率区使得匹配网络的设计简化为基频匹配网络的设计,降低了对谐波阻抗匹配的难度和宽带匹配网络设计的复杂度。实验结果表明:在1GHz -3GHz 工作频带(相对带宽100%)内,功率附加效率在53%-64.6%之间,输出功率为39.5±2dBm,增益为11.5±2dB,二次谐波小于-15dBc,三次谐波小于-25dBc。     

C波段高效率逆F类GaN MMIC功率放大器

为了解决晶体管寄生参数对逆F(F-1)类功率放大器效率的影响,采用了一种新型的输出谐波控制结构。首先,设计二次和三次谐波控制电路,同时将直流偏置电路加入二次谐波控制电路,降低了电路设计的复杂度。其次,为了解决寄生参数对F-1类功放本征漏极端阻抗的影响,采用一段串行微带线进行寄生补偿。最后,通过微带线和电容进行基波和负载之间的匹配。为验证方法的有效性,采用0.25 μm氮化镓高电子迁移率晶体管(GaN HEMT)工艺,设计了一款工作在5.7 GHz~6.3 GHz的F-1类微波集成电路功放。版图后仿真结果显示,F-1类功放的漏极效率DE为57.2%~62.3%,功率附加效率PAE为51.8%~57.4%,饱和输出功率为39.0 dBm~40.4 dBm,增益为9.0 dBm~10.4 dBm。版图面积为3.2×1.7 mm²。     

S波段高效F类/逆F类GaN HEMT功率放大器设计

为了解决F类和逆F类（F-1类）功率放大器设计过程中受晶体管寄生参数影响,导致功放效率低以及输出匹配电路结构复杂的问题,提出了一种新型的输出匹配电路结构.首先,在直流偏置线中加入谐波调谐功能,避免单独设计谐波控制电路;其次,为满足F类和F-1类功放在器件本征漏极端所需的阻抗状态,匹配寄生参数呈现的封装端谐波阻抗,采用一段L型传输线结构代替传统的L-C集总元件寄生补偿方法;最后,由两段串联的传输线实现最优基波阻抗与50 Ω负载间的匹配.为验证方法的有效性,采用CGH40010氮化镓高电子迁移率晶体管（Gallium nitride high electron mobility transistor,GaN HEMT）器件,设计并加工了两款工作在2.4 GHz的F类和F-1类功放.测试结果显示:F类功放的峰值功率附加效率（power added efficiency,PAE）为75.5%,饱和输出功率为40.8 dBm;F-1类功放的峰值PAE为77.6%,饱和输出功率为40.3 dBm.该方法降低了电路复杂度和设计难度,可以较容易地补偿晶体管寄生参数,功放在高频工作时的效率得到提升,为利用GaN HEMT器件设计高效功放提供了一种可行的方案.     

应用于4G-LTE无线通信系统的F类高PAE射频功率放大器

为了有效实现高谐波抑制并提高功率附加效率,提出了一种适用于4G-LTE无线通信系统的高效F类功率放大器。该功率放大器使用了低电压p-HEMT晶体管和小型微带抑制单元,能够在低射频输入功率下产生n次谐波抑制和较高的功率附加效率（power added efficiency,PAE）。采用谐波平衡法对提出的功率放大器进行了仿真分析,并对其进行了实际制造。通过实际测量对仿真结果进行了验证。测量结果显示,提出功率放大器的工作频率为1.8 GHz,带宽为100 MHz,平均PAE为76.9％,且具有2V的极低漏极电压。射频输入功率范围分别为0-12 dBm时,最大输出功率和增益分别为23.4和17.5 dBm。     

应用于S频段的宽带高谐波抑制的F类功率放大器的设计

采用InGaP/GaAs HBT工艺设计了一个适用于S频段的宽带F类功率放大器,管芯大小为3×3×0.82mm3。为了同时实现高谐波抑制和宽带,在宽带匹配电路中使用了谐波陷波器。在1.8~2.5 GHz范围内,该匹配网络的输入阻抗约为一个常电阻,二次谐波阻抗约为零而三次谐波阻抗接近无穷大,因此提高了功率放大器的效率。输入测试信号为连续波,测试结果表明该功率放大器在1dB压缩点下的输出功率约为34dBm,PAE约为57%,2到4次谐波分量功率均小于-53dBc。     

基于电源调制的L波段高性能GaAs HBT功率放大器

介绍了一种基于GaInP/GaAs异质结双极晶体管(HBT)工艺、电源调制的高峰均比、高功率附加效率L波段功率放大器芯片，可满足多载波聚合、大容量通信系统的要求。从器件层面控制基极表面复合、寄生电阻和电容，实现低膝点电压、跨导均匀的晶体管；在电路层面采用自适应偏置电路和谐波调谐等提升线性和功率附加效率。该放大器采用前级驱动加末级输出、驱动比为1∶6的两级晶体管架构和高低通搭配的匹配电路。测试结果表明，在5 V偏置电压下，该功率放大器的饱和输出功率大于35 dBm;在大功率回退时(8 dBm),增益变化小于2 dB,功率附加效率指标达到50%;对于调制带宽为25 kHz的16进制正交振幅调制(16QAM)通信系统，邻道功率比小于-38 dBc@27 dBm。     

基于多谐波双向牵引技术的微波功率放大器设计

功率放大器的输出功率和附加效率是设计的重点和难点,而功放设计通常采用的是负载牵引技术,强调了负载阻抗对电路输出功率和效率的影响,却常常忽略了源阻抗对它的影响.文中结合实例,介绍了基于谐波平衡分析的多谐波双向牵引优化技术的原理和实现方法.优化源和负载各谐波阻抗,仿真和实测结果表明:多谐波双向牵引优化技术能够在获得功率放大器所需的最大输出功率和最佳附加效率之间取得折中和平衡,从而满足工程设计指标要求.     

基于EFJ模式的宽带高效率Doherty功率放大器设计

将EFJ模式功率放大器应用于Doherty功率放大器的载波功率放大器,利用EFJ类功率放大器的阻抗特性改善了Doherty功率放大器的带宽。此外,还引入后谐波控制网络来提高Doherty功率放大器的效率。功放的输入匹配电路采用阶跃式阻抗匹配来进一步拓展工作带宽。使用CGH40010F GaN 晶体管设计并加工完成了一款宽带高效率Doherty功率放大器。测试结果显示,在3.2~3.7GHz 频段内,饱和输出功率达到43dBm,饱和漏极效率60%~72.5%,增益大于10dB。功率回退6dB时,漏极效率40%~48.5%。     

放大器的新型谐波匹配网络的研究与实现

在现代通信系统中,功率放大器起着重要的作用并消耗大量的功率,因此,提高放大器效率对于节约整个系统的能量是尤为重要的。本文的目标是找到放大器在谐波频率处的匹配阻抗,并最终构建放大器的谐波匹配网络,以使放大器达到其最高效率。本文采用了负载牵引技术,使用自动控制调节器对阻抗进行控制。首先对自动调谐器进行校准,得出其内部的不同坐标与相应阻抗的对应关系。然后通过对自动调谐器的控制来控制和改变二次谐波和三次谐波的负载阻抗,找到谐波匹配阻抗以使放大器在基频的效率达到最大。最终,根据谐波匹配阻抗来构建放大器的谐波匹配网络。实验结果表明：通过过谐波匹配,可以使放大器的效率提高2.13%。采用本文所使用的方法,放大器的功率提高了2.13%,实现了通过谐波匹配网络来提高放大器效率的目标,证明了本文所采用的方法的可行性。     

Multilevel outphasing system using six-port modulators and doherty power amplifiers

In this paper, a simple and efficient architecture for implementation of multilevel outphasing systems is presented. The architecture consists of a six-port modulator and a Doherty power amplifier in each outphasing branch. Pin diodes are used as variable impedances of the six-port modulator and their parasitic elements are analytically compensated. A prototype of the variable load is fabricated and the results show the effectiveness of compensation method to prepare pin diodes as variable loads for a six-port modulator. As a proof of concept, a standard 2.4 GHz Doherty power amplifier is designed with 65% efficiency at peak power and 46% efficiency at 6 dB back off. The proposed system is simulated in advanced design system using a 20 MHz WLAN signal with 7.5 dB PAPR and 5 level outphasing. Simulation results show 31.6% power added efficiency for the Doherty-Outphasing system.     

An efficient Schottky-varactor frequency multiplier at millimeter waves. Part II: Tripler

The multiplication efficiency of millimeter wave triplers was studied. In the case of a commercially available Schottky-varactor, the tripler efficiency versus pump power, bias voltage, and embedding impedances at the fundamental and harmonic frequencies was simulated using a nonlinear analysis program. A scaled model of a waveguide mount was used to experimentally optimize the impedances. For experimental verification a tripler from 33–39 GHz to 99–117 GHz was constructed. The highest efficiency measured was 28% at 107 GHz with 5 mW input power. The highest efficiency obtained with 30 mW input power was 18%.     

An efficient Schottky-varactor frequency multiplier at millimeter waves. Part I: Doubler

The efficiency of millimeter wave doublers with a wide tunable bandwidth was studied. The efficiency depends on the varactor parameters and the embedding impedances seen by the diode at fundamental and harmonic frequencies. Millimeter wave doublers were simulated with a nonlinear analysis program to find optimum embedding impedances for a given diode. Also the sensitivity of the efficiency to various diode and circuit parameters was evaluated. A scaled model was constructed in order to experimentally optimize the impedances. For experimental verification a doubler from 40–58 GHz to 80–116 GHz was constructed. The highest efficiency measured was 45% at 94 GHz with 5 mW input power. The highest efficiency obtained with 20 mW input power was 38%.     

A Novel Quasi-Optical Frequency Multiplier Design for Millimeter and Submillimeter Wavelengths

This paper describes a novel design for millimeter and sub-millimeter wavelength varactor frequency triplers and quadruplers. The varactor diode is coupled to the pump source via waveguide and stripline impedance matching and filtering structures. Output power at the various harmonics of the pump frequency is fed to quasi-optical filtering and tuning elements. The low-loss quasi-optical structures enable near-optimum control of the impedances seen by the varactor diode at the idler and output frequencies, resulting in efficient high-order harmonic conversion. A minimum efficiency of 4 percent with 30-mW input power has been obtained for a tripler operating between 200 and 280 GHz, with a peak efficiency of 8 percent between 250 and 280 GHz. Another tripler, designed for the 260-350-GHz band, gave a minimum conversion efficiency of 3 percent with 30-mW input power, with a peak efficiency of 5 percent at 340 GHz.     

Multiharmonic source-pull/load-pull active setup based on six-port reflectometers: influence of the second harmonic source impedance on RF performances of power transistors

An original measurement system for nonlinear RF power-transistor characterization is presented. This new setup enables the measurement and optimization of output power and/or power-added efficiency (PAE) using active harmonic tuning and six-port reflectometers as vector network analyzers. Two active loops are inserted at both ports of transistors in order to independently control the source and load impedances at the fundamental and at the second harmonic frequency. To the authors' knowledge, this is the only active technique that allows a complete automated multiharmonic load-pull/source-pull measurement system. Experimental results are shown for a commercial GaAs MESFET power transistor at 2 GHz.     

一种基于阻抗缓冲匹配技术的高效率Doherty放大器

为了在功率回退时满足功率放大器对高效率的要求,提出了一种采用阻抗缓冲匹配技术的Doherty功率放大器。通过负载牵引仿真,得到功放管的最佳基波和谐波负载阻抗。在此基础上,采用一种谐波控制阻抗匹配网络设计方法来设计主/辅路放大器的输出匹配网络,实现了高回退效率。为了验证该方法的有效性,设计并实现了一个1.635 GHz高效率Doherty功率放大器。测试结果表明,该放大器的饱和功率大于44 dBm,峰值效率为75%,6 dB功率回退时的效率为70%。该方法能有效提高Doherty功率放大器的回退效率。     

Extraction Technique of Differential Second Harmonic Output in CMOS LC VCO

A technique to extract differential second harmonic output signals in a CMOS LC voltage-controlled oscillator (VCO) is introduced. In a cross-coupled n-type field effect transistor (NFET) and p-channel field effect transistor (PFET) VCO topology, the upper and lower common source nodes of the FET pairs can provide well-balanced differential second harmonic output by resonating the impedances at the common source nodes and operating the VCO in the voltage-limited regime. The idea is verified experimentally by implementing a 5.6-GHz CMOS VCO having a tunable impedance element at the common source node. The error signal power between the differential signals is measured to be -70dBm when properly tuned, which indicates almost perfect differentiality of the second harmonic output signals     

High Efficiency RF Power Amplifier Designed With Harmonic Real-Time Active Load-Pull

In this work, a high efficiency p-HEMT radio frequency power amplifier (PA) is designed using a new multiharmonic real-time active load-pull using the large signal network analyzer. This technique synthesizes a large set of instantaneous load mismatches to quickly find the optimal harmonic impedances, so as to achieve high PA efficiency in a shortened design cycle. At 2 GHz a demo power amplifier implemented with a p-HEMT demonstrated a power added efficiency (PAE) of 68.5% for 18.0 dBm output power, while achieving a maximum PAE of 75% below the 1 dB compression point for 18.6 dBm output power.