Single-pair bulk-driven CMOS input stage: A compact low-voltage analog cell for scaled technologies

Bulk-driven MOS transistors lead to a compact low-voltage/low-power input stage implementation. This paper illustrates the rail-to-rail capability of a single-pair bulk-driven CMOS input stage operated from an extremely low supply voltage. A composite input stage is also introduced to point out some limitations inherent in multiple-pair input stages and carry out performance comparison, based on experimental data obtained in standard 0.35 μm CMOS technology. The performance achieved by the single-pair bulk-driven input stage can be readily extended to a nanoscale process, as lower supply voltages in scaled technologies are expected. Measurements demonstrate the rail-to-rail suitability of the single-pair input stage and show intrinsic advantages of this approach in some amplifier features, such as linearity and common-mode rejection ratio, as compared to the case of the composite solution.     

84dB动态范围13b/400kHz/3V/5.88mW ΣΔ模数转换器

介绍了一个200kHz信号带宽、用于低中频结构GSM射频接收机的高精度ΣΔ调制器. 为了达到高线性和稳定性,调制器采用2-1级联单比特的结构实现. 电路在0.18μm CMOS工艺下流片验证,核心面积为0.5mm×1.1mm. 调制器工作在19.2MHz的采样频率,在3V电源电压下功耗为5.88mW. 测试结果表明,在200kHz信号带宽,过采样率为64的条件下,调制器达到84.4dB动态范围,峰值SNDR达到73.8dB,峰值SNR达到80dB.     

A sub 1 V high PSRR CMOS bandgap voltage reference

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst case over temperature range −40 to 140°C, 60 ppm/V of supply voltage dependence and 60 dB PSRR at 1 MHz without trimming or extra circuits for the curvature compensation. The entire circuit occupies 0.027 mm² of die area and consumes from a 1.2 V supply voltage at room temperature. Twenty chips are tested to show the robustness of the topology and the measurement results are compared with Monte Carlo simulation and analysis.     

Design of Monolithic Tunable CMOS Band-Pass Filter Using Current Feedback Operational Amplifiers

We propose in this paper a tunable second order band-pass filter based on two CMOS current feedback operational amplifiers (CFOAs). The CFOA includes a novel offset compensation technique. A digital building block is implemented in the proposed band-pass filter to tune its central frequency. An important feature of the adopted tuning procedure is the ability to tune the filter without affecting other characteristics such as gain, phase and quality factor. The band-pass filter topology is validated with a configuration where the central frequency is tuned from 60 MHz to 95 MHz with frequency steps of 5 MHz. Measurements of the offset-compensated CFOA are promising, and simulation results of the CFOA-based band-pass filter using the 0.18 μ m CMOS process confirm our theoretical analysis.     

A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS

A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65 nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are −0.4/0.4 LSBs and −0.9/0.8 LSBs, respectively. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V supply. The proposed SAR ADC?s SNDR and SFDR are 49.5 dB and 64.2 dB, respectively.     

Electro-thermal characterization of a differential temperature sensor in a 65 nm CMOS IC: Applications to gain monitoring in RF amplifiers

This paper reports on the design solutions and the different measurements we have done in order to characterize the thermal coupling and the performance of differential temperature sensors embedded in an integrated circuit implemented in a 65 nm CMOS technology. The on-chip temperature increases have been generated using diode-connected MOS transistors behaving as heat sources. Temperature measurements performed with the embedded sensor are corroborated with an infra-red camera and a laser interferometer used as thermometer. A 2 GHz linear power amplifier (PA) is as well embedded in the same silicon die. In this paper we show that temperature measurements performed with the embedded temperature sensor can be used to monitor the PA DC behavior and RF activity.